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| To all our customers Regarding the change of names mentioned in the document, such as Hitachi Electric and Hitachi XX, to Renesas Technology Corp. The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.) Accordingly, although Hitachi, Hitachi, Ltd., Hitachi Semiconductors, and other Hitachi brand names are mentioned in the document, these names have in fact all been changed to Renesas Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. Renesas Technology Home Page: http://www.renesas.com Renesas Technology Corp. Customer Support Dept. April 1, 2003 Cautions Keep safety first in your circuit designs! 1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corporation product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corporation or a third party. 2. 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Please contact Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corporation is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corporation for further details on these materials or the products contained therein. H8/3627 Series H8/3627 H8/3626 H8/3625 H8/3624S H8/3623S H8/3622S HD6433627, HD6473627 HD6433626 HD6433625 HD6433624S HD6433623S HD6433622S Hardware Manual ADE-602-174 Rev. 1.0 3/5/03 Hitachi, Ltd. MC-Setsu Cautions 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi's or any third party's patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party's rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However, contact Hitachi's sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi. 7. Contact Hitachi's sales office for any questions regarding this document or Hitachi semiconductor products. Preface The H8/300L Series of single-chip microcomputers has a high-speed H8/300L CPU core, with many necessary peripheral system functions on-chip. The H8/300L CPU instruction set is compatible with the H8/300 CPU. On-chip peripheral functions of the H8/3627 Series include a high-precision DTMF generator for tone dialing, three types of timers, two serial communication interface channels, and an A/D converter. This manual describes the hardware of the H8/3627 Series. For details on the H8/3627 Series instruction set, refer to the H8/300L Series Programming Manual. Contents Section 1 1.1 1.2 1.3 Overview ........................................................................................................... Overview............................................................................................................................ Internal Block Diagram ..................................................................................................... Pin Arrangement and Functions ........................................................................................ 1.3.1 Pin Arrangement .................................................................................................. 1.3.2 Pin Functions........................................................................................................ 1 1 5 6 6 7 Section 2 2.1 CPU..................................................................................................................... 11 11 11 12 12 13 13 13 15 15 16 17 18 18 20 24 26 28 29 29 31 35 37 38 40 40 41 42 42 44 44 44 i 2.2 2.3 2.4 2.5 2.6 2.7 Overview............................................................................................................................ 2.1.1 Features ................................................................................................................ 2.1.2 Address Space ...................................................................................................... 2.1.3 Register Configuration ......................................................................................... Register Descriptions......................................................................................................... 2.2.1 General Registers.................................................................................................. 2.2.2 Control Registers.................................................................................................. 2.2.3 Initial Register Values .......................................................................................... Data Formats...................................................................................................................... 2.3.1 Data Formats in General Registers....................................................................... 2.3.2 Memory Data Formats.......................................................................................... Addressing Modes ............................................................................................................. 2.4.1 Addressing Modes................................................................................................ 2.4.2 Effective Address Calculation.............................................................................. Instruction Set.................................................................................................................... 2.5.1 Data Transfer Instructions .................................................................................... 2.5.2 Arithmetic Operations .......................................................................................... 2.5.3 Logic Operations .................................................................................................. 2.5.4 Shift Operations.................................................................................................... 2.5.5 Bit Manipulations ................................................................................................. 2.5.6 Branching Instructions.......................................................................................... 2.5.7 System Control Instructions ................................................................................. 2.5.8 Block Data Transfer Instruction ........................................................................... Basic Operational Timing.................................................................................................. 2.6.1 Access to On-Chip Memory (RAM, ROM) ......................................................... 2.6.2 Access to On-Chip Peripheral Modules ............................................................... CPU States ......................................................................................................................... 2.7.1 Overview .............................................................................................................. 2.7.2 Program Execution State ...................................................................................... 2.7.3 Program Halt State ............................................................................................... 2.7.4 Exception-Handling State .................................................................................... 2.8 2.9 Memory Map ..................................................................................................................... 45 Application Notes.............................................................................................................. 46 2.9.1 Notes on Data Access........................................................................................... 46 2.9.2 Notes on Bit Manipulation ................................................................................... 48 2.9.3 Notes on Use of the EEPMOV Instruction .......................................................... 54 Section 3 3.1 3.2 Exception Handling........................................................................................ 55 3.3 3.4 Overview............................................................................................................................ 55 Reset .................................................................................................................................. 55 3.2.1 Overview .............................................................................................................. 55 3.2.2 Reset Sequence..................................................................................................... 55 3.2.3 Interrupt Immediately after Reset ........................................................................ 56 Interrupts............................................................................................................................ 57 3.3.1 Overview .............................................................................................................. 57 3.3.2 Interrupt Control Registers ................................................................................... 59 3.3.3 External Interrupts................................................................................................ 67 3.3.4 Internal Interrupts ................................................................................................. 67 3.3.5 Interrupt Operations.............................................................................................. 68 3.3.6 Interrupt Response Time ...................................................................................... 73 Application Notes.............................................................................................................. 74 3.4.1 Notes on Stack Area Use...................................................................................... 74 3.4.2 Notes on Rewriting Port Mode Registers............................................................. 74 Section 4 4.1 4.2 4.3 4.4 4.5 Clock Pulse Generators................................................................................. 77 Overview............................................................................................................................ 77 4.1.1 Block Diagram...................................................................................................... 77 4.1.2 System Clock and Subclock ................................................................................. 77 System Clock Generator.................................................................................................... 78 Subclock Generator ........................................................................................................... 81 Prescalers ........................................................................................................................... 82 Note on Oscillators ............................................................................................................ 82 85 85 88 91 91 91 92 92 92 93 94 Section 5 5.1 5.2 5.3 Power-Down Modes ...................................................................................... Overview............................................................................................................................ 5.1.1 System Control Registers ..................................................................................... Sleep Mode........................................................................................................................ 5.2.1 Transition to Sleep Mode ..................................................................................... 5.2.2 Clearing Sleep Mode ............................................................................................ Standby Mode.................................................................................................................... 5.3.1 Transition to Standby Mode ................................................................................. 5.3.2 Clearing Standby Mode........................................................................................ 5.3.3 Oscillator Settling Time after Standby Mode is Cleared...................................... 5.3.4 Transition to Standby Mode and Pin States ......................................................... ii 5.4 5.5 5.6 5.7 5.8 Watch Mode ...................................................................................................................... 5.4.1 Transition to Watch Mode.................................................................................... 5.4.2 Clearing Watch Mode .......................................................................................... 5.4.3 Oscillator Settling Time after Watch Mode is Cleared ........................................ Subsleep Mode .................................................................................................................. 5.5.1 Transition to Subsleep Mode................................................................................ 5.5.2 Clearing Subsleep Mode ...................................................................................... Subactive Mode ................................................................................................................. 5.6.1 Transition to Subactive Mode .............................................................................. 5.6.2 Clearing Subactive Mode ..................................................................................... 5.6.3 Operating Frequency in Subactive Mode ............................................................. Active (medium-speed) Mode ........................................................................................... 5.7.1 Transition to Active (medium-speed) Mode ........................................................ 5.7.2 Clearing Active (medium-speed) Mode ............................................................... 5.7.3 Operating Frequency in Active (medium-speed) Mode....................................... Direct Transfer................................................................................................................... 5.8.1 Overview .............................................................................................................. 5.8.2 Direct Transfer Time ............................................................................................ 95 95 95 95 96 96 96 97 97 97 97 98 98 98 98 99 99 100 103 103 103 104 104 104 107 108 112 113 Section 6 6.1 6.2 6.3 6.4 ROM ................................................................................................................... Overview............................................................................................................................ 6.1.1 Block Diagram...................................................................................................... PROM Mode...................................................................................................................... 6.2.1 Selection of PROM Mode .................................................................................... 6.2.2 Socket Adapter Pin Arrangement and Memory Map ........................................... Programming ..................................................................................................................... 6.3.1 Programming and Verification ............................................................................. 6.3.2 Programming Precautions .................................................................................... Reliability of Programmed Data........................................................................................ Section 7 7.1 RAM ................................................................................................................... 115 Overview............................................................................................................................ 115 7.1.1 Block Diagram...................................................................................................... 115 Section 8 8.1 8.2 I/O Ports ............................................................................................................ 117 117 119 119 119 123 124 125 126 iii 8.3 Overview............................................................................................................................ Port 1.................................................................................................................................. 8.2.1 Overview .............................................................................................................. 8.2.2 Register Configuration and Description............................................................... 8.2.3 Pin Functions........................................................................................................ 8.2.4 Pin States .............................................................................................................. 8.2.5 MOS Input Pull-Up .............................................................................................. Port 2.................................................................................................................................. 8.4 8.5 8.6 8.7 8.8 8.9 8.3.1 Overview .............................................................................................................. 8.3.2 Register Configuration and Description............................................................... 8.3.3 Pin Functions........................................................................................................ 8.3.4 Pin States .............................................................................................................. 8.3.5 MOS Input Pull-Up .............................................................................................. Port 5.................................................................................................................................. 8.4.1 Overview .............................................................................................................. 8.4.2 Register Configuration and Description............................................................... 8.4.3 Pin Functions........................................................................................................ 8.4.4 Pin States .............................................................................................................. 8.4.5 MOS Input Pull-Up .............................................................................................. Port 6.................................................................................................................................. 8.5.1 Overview .............................................................................................................. 8.5.2 Register Configuration and Description............................................................... 8.5.3 Pin Functions........................................................................................................ 8.5.4 Pin States .............................................................................................................. 8.5.5 MOS Input Pull-Up .............................................................................................. Port 7.................................................................................................................................. 8.6.1 Overview .............................................................................................................. 8.6.2 Register Configuration and Description............................................................... 8.6.3 Pin Functions........................................................................................................ 8.6.4 Pin States .............................................................................................................. Port 8.................................................................................................................................. 8.7.1 Overview .............................................................................................................. 8.7.2 Register Configuration and Description............................................................... 8.7.3 Pin Functions........................................................................................................ 8.7.4 Pin States .............................................................................................................. Port A................................................................................................................................. 8.8.1 Overview .............................................................................................................. 8.8.2 Register Configuration and Description............................................................... 8.8.3 Pin Functions........................................................................................................ 8.8.4 Pin States .............................................................................................................. Port B ................................................................................................................................. 8.9.1 Overview .............................................................................................................. 8.9.2 Register Configuration and Description............................................................... 126 126 131 133 133 134 134 134 136 137 137 138 138 138 140 140 140 141 141 141 143 143 144 144 144 146 146 147 147 147 149 149 150 150 150 151 151 152 152 153 155 156 Section 9 9.1 9.2 Timers ................................................................................................................ Overview............................................................................................................................ Timer A.............................................................................................................................. 9.2.1 Overview .............................................................................................................. 9.2.2 Register Descriptions............................................................................................ 9.2.3 Timer Operation ................................................................................................... 9.2.4 Timer A Operation States..................................................................................... iv 9.3 9.4 Timer F .............................................................................................................................. 9.3.1 Overview .............................................................................................................. 9.3.2 Register Descriptions............................................................................................ 9.3.3 Interface with the CPU ......................................................................................... 9.3.4 Timer Operation ................................................................................................... 9.3.5 Application Notes................................................................................................. Timer G.............................................................................................................................. 9.4.1 Overview .............................................................................................................. 9.4.2 Register Descriptions............................................................................................ 9.4.3 Noise Canceller Circuit ........................................................................................ 9.4.4 Timer Operation ................................................................................................... 9.4.5 Application Notes................................................................................................. 9.4.6 Sample Timer G Application................................................................................ 157 157 159 166 169 171 173 173 175 179 180 184 188 Section 10 Serial Communication Interface ................................................................ 189 10.1 Overview............................................................................................................................ 189 10.2 SCI1 ................................................................................................................................... 189 10.2.1 Overview .............................................................................................................. 189 10.2.2 Register Descriptions............................................................................................ 191 10.2.3 Operation .............................................................................................................. 195 10.2.4 Interrupt Sources .................................................................................................. 197 10.3 SCI3 ................................................................................................................................... 198 10.3.1 Overview .............................................................................................................. 198 10.3.2 Register Descriptions............................................................................................ 200 10.3.3 Operation .............................................................................................................. 217 10.3.4 Operation in Asynchronous Mode........................................................................ 222 10.3.5 Operation in Synchronous Mode.......................................................................... 230 10.3.6 Multiprocessor Communication Function............................................................ 238 10.3.7 Interrupts .............................................................................................................. 244 10.3.8 Application Notes................................................................................................. 245 Section 11 DTMF Generator ............................................................................................ 249 11.1 Overview............................................................................................................................ 11.1.1 Features ................................................................................................................ 11.1.2 Block Diagram...................................................................................................... 11.1.3 Pin Configuration ................................................................................................. 11.1.4 Register Configuration ......................................................................................... 11.2 Register Descriptions......................................................................................................... 11.2.1 DTMF Control Register (DTCR) ......................................................................... 11.2.2 DTMF Load Register (DTLR) ............................................................................. 11.3 Operation ........................................................................................................................... 11.3.1 Output Waveform................................................................................................. 11.3.2 Operation Flow..................................................................................................... 249 250 251 252 252 253 253 255 256 256 257 v 11.4 Typical Use........................................................................................................................ 258 11.5 Application Notes.............................................................................................................. 258 Section 12 A/D Converter ................................................................................................. 259 12.1 Overview............................................................................................................................ 12.1.1 Features ................................................................................................................ 12.1.2 Block Diagram...................................................................................................... 12.1.3 Pin Configuration ................................................................................................. 12.1.4 Register Configuration ......................................................................................... 12.2 Register Descriptions......................................................................................................... 12.2.1 A/D Result Register (ADRR)............................................................................... 12.2.2 A/D Mode Register (AMR).................................................................................. 12.2.3 A/D Start Register (ADSR).................................................................................. 12.3 Operation ........................................................................................................................... 12.3.1 A/D Conversion Operation................................................................................... 12.3.2 Start of A/D Conversion by External Trigger Input............................................. 12.4 Interrupts............................................................................................................................ 12.5 Typical Use........................................................................................................................ 12.6 Application Notes.............................................................................................................. 259 259 260 260 261 261 261 262 263 264 264 264 265 265 268 Section 13 Power Supply Circuit .................................................................................... 269 13.1 Overview............................................................................................................................ 269 13.2 Internal Power Supply Step-Down Circuit Formats.......................................................... 269 Section 14 Electrical Characteristics.............................................................................. 271 14.1 Absolute Maximum Ratings.............................................................................................. 14.2 Electrical Characteristics ................................................................................................... 14.2.1 Power Supply Voltage and Operating Range....................................................... 14.2.2 DC Characteristics................................................................................................ 14.2.3 AC Characteristics................................................................................................ 14.2.4 A/D Converter Characteristics ............................................................................. 14.2.5 DTMF Characteristics .......................................................................................... 14.3 Operation Timing .............................................................................................................. 14.4 Output Load Circuits ......................................................................................................... 271 272 272 274 279 282 283 284 287 Appendix A CPU Instruction Set ................................................................................... 289 A.1 A.2 A.3 Instructions ........................................................................................................................ 289 Operation Code Map.......................................................................................................... 297 Number of Execution States.............................................................................................. 299 Appendix B On-Chip Registers ...................................................................................... 306 B.1 B.2 vi I/O Registers (1) ................................................................................................................ 306 I/O Registers (2) ................................................................................................................ 310 Appendix C I/O Port Block Diagrams.......................................................................... 344 C.1 C.2 C.3 C.4 C.5 C.6 C.7 C.8 Port 1 Block Diagrams ...................................................................................................... Port 2 Block Diagrams ...................................................................................................... Port 5 Block Diagram........................................................................................................ Port 6 Block Diagram........................................................................................................ Port 7 Block Diagram........................................................................................................ Port 8 Block Diagram........................................................................................................ Port A Block Diagram ....................................................................................................... Port B Block Diagram ....................................................................................................... 344 351 359 360 361 362 363 363 Appendix D Port States in the Different Processing States.................................... 364 Appendix E Appendix F Product Line-Up.......................................................................................... 365 Package Dimensions.................................................................................. 366 vii Section 1 Overview 1.1 Overview The H8/300L Series is a series of single-chip microcomputers (MCU: microcomputer unit), built around the high-speed H8/300L CPU and equipped with peripheral system functions on-chip. Within the H8/300L Series, the H8/3627 Series of single-chip microcomputers features a highprecision DTMF generator for tone dialing. Other on-chip peripheral functions include three types of timers, two serial communication interface channels, and an A/D converter. The H8/3627 Series includes six models, the H8/3627, H8/3626, H8/3625, H8/3624, H8/3623, and H8/3622, with different amounts of on-chip memory: the H8/3627 has 60 kbytes of ROM and 2 kbytes of RAM; the H8/3626 has 48 kbytes of ROM and 2 kbytes of RAM; the H8/3625 has 40 kbytes of ROM and 2 kbytes of RAM; the H8/3624S has 32 kbytes of ROM and 1 kbyte of RAM; the H8/3623S has 24 kbytes of ROM and 1 kbyte of RAM; and the H8/3622S has 16 kbytes of ROM and 1 kbyte of RAM. In addition, thanks to the improvement of the power supply circuit, low power consumption and low radiation noise have been realized. The H8/3627 has a ZTAT* version with user-programmable on-chip PROM. Table 1.1 summarizes the features of the H8/3627 Series. Note: * ZTAT TM is a trademark of Hitachi, Ltd. 1 Table 1.1 Item CPU Features Description High-speed H8/300L CPU * General-register architecture General registers: Sixteen 8-bit registers (can be used as eight 16-bit registers) * Operating speed Max. operating speed: 5 MHz Add/subtract: 0.4 s (operating at o= 5 MHz) Multiply/divide: 2.8 s (operating at o= 5 MHz) Can run on 32.768 kHz subclock * Instruction set compatible with H8/300 CPU Instruction length of 2 bytes or 4 bytes Basic arithmetic operations between registers MOV instruction for data transfer between memory and registers * Instruction features Multiply (8 bits x 8 bits) Divide (16 bits / 8 bits) Bit accumulator Register-indirect designation of bit position Interrupts 29 interrupt sources * * 13 external interrupt sources: IRQ4 to IRQ 0, WKP 7 to WKP0 16 internal interrupt sources Clock pulse generators Two on-chip clock pulse generators * * System clock pulse generator: 1 MHz to 10 MHz Subclock pulse generator: 32.768 kHz Power-down modes Six power-down modes * * * * * * Sleep mode Standby mode Watch mode Subsleep mode Subactive mode Active (medium-speed) mode 2 Table 1.1 Item Memory Features (cont) Description Large on-chip memory * * * * * * H8/3627: H8/3626: H8/3625: 60-kbyte ROM, 2-kbyte RAM 48-kbyte ROM, 2-kbyte RAM 40-kbyte ROM, 2-kbyte RAM H8/3624S: 32-kbyte ROM, 1-kbyte RAM H8/3623S: 24-kbyte ROM, 1-kbyte RAM H8/3622S: 16-kbyte ROM, 1-kbyte RAM I/O ports 53 I/O ports * * I/O pins: 50 Input pins: 3 Timers 3 on-chip timers * Timer A: 8-bit timer with built-in interval/watch clock time base function Count-up timer with selection of eight internal clock signals divided from the system clock (o)* and four clock signals divided from the watch clock (ow)* * Timer F: 16-bit timer with built-in output compare function Can be used as two independent 8-bit timers. Count-up timer with selection of four internal clock signals or event input from external pin Compare-match function with toggle output * Timer G: 8-bit timer with built-in input capture/interval functions Count-up timer with selection of four internal clock signals Input capture function with built-in noise canceller circuit Serial communication interface Two serial communication interface channels on chip * * SCI1: synchronous serial interface Choice of 8-bit or 16-bit data transfer SCI3: 8-bit synchronous or asynchronous serial interface Built-in function for multiprocessor communication Note: * o and ow are defined in section 4, Clock Pulse Generators. 3 Table 1.1 Item Features (cont) Description 8-bit successive-approximations A/D converter using a resistance ladder * * 2-channel analog input port Conversion time: 31/o, 62/o or 124/o per channel A/D converter DTMF generator Product lineup Built-in tone dialer supporting OSC clock frequencies from 1.2 MHz to 10 MHz in 400-kHz steps Product Code Mask ROM Version HD6433627H HD6433627FP HD6433626H HD6433626FP HD6433625H HD6433625FP HD6433624SH HD6433624SFP HD6433623SH HD6433623SFP HD6433622SH HD6433622SFP ZTATTM Version HD6473627H HD6473627FP -- -- -- -- -- -- -- -- -- -- Package 64-pin QFP (FP-64A) 64-pin LQFP (FP-64E) 64-pin QFP (FP-64A) 64-pin LQFP (FP-64E) 64-pin QFP (FP-64A) 64-pin LQFP (FP-64E) 64-pin QFP (FP-64A) 64-pin LQFP (FP-64E) 64-pin QFP (FP-64A) 64-pin LQFP (FP-64E) 64-pin QFP (FP-64A) 64-pin LQFP (FP-64E) ROM: 16 kbytes RAM: 1 kbyte ROM: 24 kbytes RAM: 1 kbyte ROM: 32 kbytes RAM: 1 kbyte ROM: 40 kbytes RAM: 2 kbytes ROM: 48 kbytes RAM: 2 kbytes ROM/RAM Size ROM: 60 kbytes RAM: 2 kbytes 4 1.2 Internal Block Diagram Figure 1.1 shows a block diagram of the H8/3627 Series. OSC2 OSC1 X1 X2 System clock pulse generator Subclock pulse generator Data bus (upper) Address bus CPU (8-bit) P10/TMOW P11/TMOFL P12/TMOFH P13/TMIG P14 P15/IRQ1 P16/IRQ2 P17/IRQ3/TMIF P20/IRQ4/ADTRG P21/SCK1 P22/SI1 P23/SO1 P24/SCK3 P25/RXD P26/TXD P27/IRQ0 P50/WKP0 P51/WKP1 P52/WKP2 P53/WKP3 P54/WKP4 P55/WKP5 P56/WKP6 P57/WKP7 P60 P61 P62 P63 P64 P65 P66 P67 Data bus (lower) Port 1 RES TEST VSS VCC CVCC ROM 16 k/24 k/ 32 k/40 k/ 48 k/60 k bytes RAM (1 k/2 kbytes) PA3 PA2 PA1 Port 2 Timer A SCI1 Timer F Port A Port 8 Timer G SCI3 P87 P86 P85 P84 P83 P82 P81 P80 P77 P76 P75 P74 P73 P72 P71 P70 Port 6 Port 5 A/D converter Port B PB6/AN6 PB7/AN7 Figure 1.1 Block Diagram TONED VTref Port 7 DTMF 5 1.3 1.3.1 Pin Arrangement and Functions Pin Arrangement The H8/3627 Series pin arrangement is shown in figure 1.2. P57/WKP7 P56/WKP6 P55/WKP5 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 X1 2 X2 3 VSS 4 OSC2 5 OSC1 6 TEST 7 VCC 8 RES 9 10 11 12 13 14 15 16 P20/IRQ4/ADTRG P21/SCK1 P24/SCK3 P27/IRQ0 P25/RXD P26/TXD P23/SO1 P22/SI1 P74 P73 P72 P71 P70 P67 P66 P65 P64 P63 P62 P61 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P75 P76 P77 P80 P81 P82 P83 P84 P85 P86 P87 TONED VTref PB7/AN7 PB6/AN6 CVCC 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 P54/WKP4 P53/WKP3 P52/WKP2 P51/WKP1 P50/WKP0 PA1 PA2 PA3 P10/TMOW P11/TMOFL P12/TMOFH P13/TMIG P14 P15/IRQ1 P16/IRQ2 P17/IRQ3/TMIF Figure 1.2 Pin Arrangement (FP-64A, FP-64E: Top View) 6 P60 1.3.2 Pin Functions Table 1.2 outlines the pin functions. Table 1.2 Pin Functions Pin No. Type Symbol FP-64A FP-64E 7 3 64 61 5 4 1 2 8 6 16 19 18 17 9 35 to 28 I/O Input Input Input Input Input Output Input Output Input Input Input Name and Functions Power supply: All V CC pins should be connected to the system power supply (+5 V) Ground: All V SS pins should be connected to the system power supply (0 V) Connected a 0.1 F stabilization capacitor between the CV CC pin and ground. DTMF generator reference level: This is a power supply pin for the reference level for DTMF. System clock: These pins connect to a crystal or ceramic oscillator, or can be used to input external an clock. See section 4, Clock Pulse Generators, for a typical connection diagram. Subclock: These pins connect to a 32.768-kHz crystal oscillator. See section 4, Clock Pulse Generators, for a typical connection diagram. Reset: When this pin is driven low, the chip is reset Test: This is a test pin, not for use in applica-tion systems. It should be connected to VSS. External interrupt request 0 to 4: These are input pins for external interrupts for which there is a choice between rising and falling edge sensing Power VCC source pins VSS CV CC VT ref Clock pins OSC 1 OSC 2 X1 X2 System control RES TEST IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 WKP 7 to WKP 0 Interrupt pins Input Wakeup interrupt request 0 to 7: These are input pins for external interrupts that are detected at the falling edge 7 Table 1.2 Pin Functions (cont) Pin No. Type Timer pins Symbol TMOW TMIF TMOFL FP-64A FP-64E 24 17 23 I/O Output Input Output Name and Functions Clock output: This is an output pin for wave-forms generated by the timer A output circuit Timer F event counter input: This is an event input pin for input to the timer F counter Timer FL output: This is an output pin for waveforms generated by the timer FL output compare function Timer FH output: This is an output pin for waveforms generated by the timer FH output compare function Timer G capture input: This is an input pin for the timer G input capture function Port B: This is a 2-bit input port Port A: This is a 3-bit I/O port. Input or output can be designated for each bit by means of port control register A (PCRA). Port 1: This is an 8-bit I/O port. Input or output can be designated for each bit be means of port control register 1 (PCR1). Port 2 (bit 7): This is a 1-bit input port. Port 2 (bits 6 to 0): This is a 7-bit I/O port. Input or output can be designated for each bit by means of port control register 2 (PCR2). Port 5: This is an 8-bit I/O port. Input or output can be designated for each bit by means of port control register 5 (PCR5). Port 6: This is an 8-bit I/O port. Input or output can be designated for each bit by means of port control register 6 (PCR6). Port 7: This is an 8-bit I/O port. Input or output can be designated for each bit by means of port control register 7 (PCR7). Port 8: This is an 8-bit I/O port. Input or output can be designated for each bit by means of port control register 8 (PCR8). TMOFH 22 Output TMIG I/O ports PB7, PB6 PA3 to PA1 P17 to P10 P27 P26 to P20 P57 to P50 P67 to P60 P77 to P70 P87 to P80 21 62 to 63 25 to 27 Input Input I/O 17 to 24 I/O 16 15 to 9 Input I/O 35 to 28 I/O 43 to 36 I/O 51 to 44 I/O 59 to 52 I/O 8 Table 1.2 Pin Functions (cont) Pin No. Type Serial communication interface (SCI) Symbol SI 1 SO1 SCK 1 RXD TXD SCK 3 FP-64A FP-64E 11 12 10 14 15 13 62, 63 9 60 I/O Input Output I/O Input Output I/O Input Input Output Name and Functions SCI1 receive data input: This is the SCI1 data input pin SCI1 send data output: This is the SCI1 data output pin SCI1 clock I/O :This is the SCI1 clock I/O pin SCI3 receive data input: This is the SCI3 data input pin SCI3 send data output: This is the SCI3 data output pin SCI3 clock I/O: This is the SCI3 clock I/O pin Analog input channels 6, 7: These are analog data input channels to the A/D converter A/D converter trigger input: This is the external trigger input pin to the A/D converter DTMF signal: This is the output pin for the DTMF signal A/D c onv erter AN 7, AN 6 ADTRG DTMF generator TONED 9 10 Section 2 CPU 2.1 Overview The H8/300L CPU has sixteen 8-bit general registers, which can also be paired as eight 16-bit registers. Its concise, optimized instruction set is designed for high-speed operation. 2.1.1 Features Features of the H8/300L CPU are listed below. * General-register architecture Sixteen 8-bit general registers, also usable as eight 16-bit general registers * Instruction set with 55 basic instructions, including: Multiply and divide instructions Powerful bit-manipulation instructions * Eight addressing modes Register direct Register indirect Register indirect with displacement Register indirect with post-increment or pre-decrement Absolute address Immediate Program-counter relative Memory indirect * 64-kbyte address space * High-speed operation All frequently used instructions are executed in two to four states High-speed arithmetic and logic operations 8- or 16-bit register-register add or subtract: 0.4 s* 8 x 8-bit multiply: 2.8 s* 16 / 8-bit divide: 2.8 s* * Low-power operation modes SLEEP instruction for transition to low-power operation Note: * These values are at o = 5 MHz. 11 2.1.2 Address Space The H8/300L CPU supports an address space of up to 64 kbytes for storing program code and data. See 2.8, Memory Map, for details of the memory map. 2.1.3 Register Configuration Figure 2.1 shows the register structure of the H8/300L CPU. There are two groups of registers: the general registers and control registers. General registers (Rn) 7 R0H R1H R2H R3H R4H R5H R6H R7H (SP) 07 R0L R1L R2L R3L R4L R5L R6L R7L SP: Stack Pointer 0 Control registers (CR) 15 PC 76543210 CCR I U H U N Z V C 0 PC: Program Counter CCR: Condition Code Register Carry flag Overflow flag Zero flag Negative flag Half-carry flag Interrupt mask bit User bit User bit Figure 2.1 CPU Registers 12 2.2 2.2.1 Register Descriptions General Registers All the general registers have the same functions, and can be used as both data registers and address registers. When used as data registers, they can be accessed as 16-bit registers (R0 to R7), or the high bytes (R0H to R7H) and low bytes (R0L to R7L) can be accessed separately as 8-bit registers. When used as address registers, the general registers are accessed as 16-bit registers (R0 to R7). R7 also functions as the stack pointer (SP), used implicitly by hardware in exception handling and subroutine calls. When it functions as the stack pointer, as indicated in figure 2.2, SP (R7) points to the top of the stack. Lower address side [H'0000] Unused area SP (R7) Stack area Upper address side [H'FFFF] Figure 2.2 Stack Pointer 2.2.2 Control Registers The CPU control registers include a 16-bit program counter (PC) and an 8-bit condition code register (CCR). (1) Program Counter (PC): This 16-bit register indicates the address of the next instruction the CPU will execute. All instructions are fetched 16 bits (1 word) at a time, so the least significant bit of the PC is ignored (always regarded as 0). 13 (2) Condition Code Register (CCR): This 8-bit register contains internal status information, including the interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. These bits can be read and written by software (using the LDC, STC, ANDC, ORC, and XORC instructions). The N, Z, V, and C flags are used as branching conditions for conditional branching (Bcc) instructions. Bit 7--Interrupt Mask Bit (I): When this bit is set to 1, interrupts are masked. This bit is set to 1 automatically at the start of exception handling. The interrupt mask bit may be read and written by software. For further details, see 3.3, Interrupts. Bit 6--User Bit (U): Can be used freely by the user. Bit 5--Half-Carry Flag (H): When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or NEG.B instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and is cleared to 0 otherwise. The H flag is used implicitly by the DAA and DAS instructions. When the ADD.W, SUB.W, or CMP.W instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 11, and is cleared to 0 otherwise. Bit 4--User Bit (U): Can be used freely by the user. Bit 3--Negative Flag (N): Indicates the most significant bit (sign bit) of the result of an instruction. Bit 2--Zero Flag (Z): Set to 1 to indicate a zero result, and cleared to 0 to indicate a non-zero result. Bit 1--Overflow Flag (V): Set to 1 when an arithmetic overflow occurs, and cleared to 0 at other times. Bit 0--Carry Flag (C): Set to 1 when a carry occurs, and cleared to 0 otherwise. Used by: * Add instructions, to indicate a carry * Subtract instructions, to indicate a borrow * Shift/rotate carry The carry flag is also used as a bit accumulator by bit manipulation instructions. Some instructions leave some or all of the flag bits unchanged. Refer to the H8/300L Series Programming Manual for the action of each instruction on the flag bits. 14 2.2.3 Initial Register Values When the CPU is reset, the program counter (PC) is initialized to the value stored at address H'0000 in the vector table, and the I bit in the CCR is set to 1. The other CCR bits and the general registers are not initialized. In particular, the stack pointer (R7) is not initialized. R7 initialization should therefore be carried out immediately after a reset. 2.3 Data Formats The H8/300L CPU can process 1-bit data, 4-bit (BCD) data, 8-bit (byte) data, and 16-bit (word) data. Bit manipulation instructions operate on 1-bit data specified as bit n in a byte operand (n = 0, 1, 2, ..., 7). All arithmetic and logic instructions except ADDS and SUBS can operate on byte data. The MOV.W, ADD.W, SUB.W, CMP.W, ADDS, SUBS, MULXU (8 bits x 8 bits), and DIVXU (16 bits / 8 bits) instructions operate on word data. The DAA and DAS instructions perform decimal arithmetic adjustments on byte data in two-digit 4-bit BCD form. 15 2.3.1 Data Formats in General Registers General register data formats are shown in figure 2.3. Data Type Register No. 7 Data Format 0 1-bit data RnH 7 6 5 4 3 2 1 0 Don't care 7 0 1-bit data RnL Don't care 7 6 5 4 3 2 1 0 7 0 LSB Byte data RnH MSB Don't care 7 0 LSB Byte data RnL Don't care MSB 15 0 LSB Word data Rn MSB 7 4 Upper digit 3 Lower digit 0 4-bit BCD data RnH Don't care 7 4 Upper digit 3 Lower digit 0 4-bit BCD data RnL Don't care Legend: RnH: Upper byte of general register RnL: Lower byte of general register MSB: Most significant bit LSB: Least significant bit Figure 2.3 Register Data Formats 16 2.3.2 Memory Data Formats Figure 2.4 indicates the data formats in memory. For access by the H8/300L CPU, word data stored in memory must always begin at an even address. In word access the least significant bit of the address is regarded as 0. If an odd address is specified, the access is performed at the preceding even address. This rule affects the MOV.W instruction, and also applies to instruction fetching. Data Type Address Data Format 7 0 1-bit data Byte data Address n Address n Even address Odd address Even address Odd address Even address Odd address 7 MSB 6 5 4 3 2 1 0 LSB Word data MSB Upper 8 bits Lower 8 bits LSB Byte data (CCR) on stack MSB MSB CCR CCR* LSB LSB Word data on stack MSB LSB CCR: Condition code register Note: * Ignored on return Figure 2.4 Memory Data Formats When the stack is accessed using R7 as an address register, word access should always be performed. When the CCR is pushed on the stack, two identical copies of the CCR are pushed to make a complete word. When they are restored, the lower byte is ignored. 17 2.4 2.4.1 Addressing Modes Addressing Modes The H8/300L CPU supports the eight addressing modes listed in table 2.1. Each instruction uses a subset of these addressing modes. Table 2.1 No. 1 2 3 4 5 6 7 8 Addressing Modes Address Modes Register direct Register indirect Register indirect with displacement Register indirect with post-increment Register indirect with pre-decrement Absolute address Immediate Program-counter relative Memory indirect Symbol Rn @Rn @(d:16, Rn) @Rn+ @-Rn @aa:8 or @aa:16 #xx:8 or #xx:16 @(d:8, PC) @@aa:8 1. Register Direct--Rn: The register field of the instruction specifies an 8- or 16-bit general register containing the operand. Only the MOV.W, ADD.W, SUB.W, CMP.W, ADDS, SUBS, MULXU (8 bits x 8 bits), and DIVXU (16 bits / 8 bits) instructions have 16-bit operands. 2. Register Indirect--@Rn: The register field of the instruction specifies a 16-bit general register containing the address of the operand in memory. 3. Register Indirect with Displacement--@(d:16, Rn): The instruction has a second word (bytes 3 and 4) containing a displacement which is added to the contents of the specified general register to obtain the operand address in memory. This mode is used only in MOV instructions. For the MOV.W instruction, the resulting address must be even. 18 4. Register Indirect with Post-Increment or Pre-Decrement--@Rn+ or @-Rn: * Register indirect with post-increment--@Rn+ The @Rn+ mode is used with MOV instructions that load registers from memory. The register field of the instruction specifies a 16-bit general register containing the address of the operand. After the operand is accessed, the register is incremented by 1 for MOV.B or 2 for MOV.W. For MOV.W, the original contents of the 16-bit general register must be even. * Register indirect with pre-decrement--@-Rn The @-Rn mode is used with MOV instructions that store register contents to memory. The register field of the instruction specifies a 16-bit general register which is decremented by 1 or 2 to obtain the address of the operand in memory. The register retains the decremented value. The size of the decrement is 1 for MOV.B or 2 for MOV.W. For MOV.W, the original contents of the register must be even. 5. Absolute Address--@aa:8 or @aa:16: The instruction specifies the absolute address of the operand in memory. The absolute address may be 8 bits long (@aa:8) or 16 bits long (@aa:16). The MOV.B and bit manipulation instructions can use 8-bit absolute addresses. The MOV.B, MOV.W, JMP, and JSR instructions can use 16-bit absolute addresses. For an 8-bit absolute address, the upper 8 bits are assumed to be 1 (H'FF). The address range is H'FF00 to H'FFFF (65280 to 65535). 6. Immediate--#xx:8 or #xx:16: The instruction contains an 8-bit operand (#xx:8) in its second byte, or a 16-bit operand (#xx:16) in its third and fourth bytes. Only MOV.W instructions can contain 16-bit immediate values. The ADDS and SUBS instructions implicitly contain the value 1 or 2 as immediate data. Some bit manipulation instructions contain 3-bit immediate data in the second or fourth byte of the instruction, specifying a bit number. 7. Program-Counter Relative--@(d:8, PC): This mode is used in the Bcc and BSR instructions. An 8-bit displacement in byte 2 of the instruction code is sign-extended to 16 bits and added to the program counter contents to generate a branch destination address. The possible branching range is -126 to +128 bytes (-63 to +64 words) from the current address. The result of the addition should be an even number. 19 8. Memory Indirect--@@aa:8: This mode can be used by the JMP and JSR instructions. The second byte of the instruction code specifies an 8-bit absolute address. The word located at this address contains the branch destination address. The upper 8 bits of the absolute address are assumed to be 0 (H'00), so the address range is H'0000 to H'00FF (0 to 255). Note that with the H8/300L Series, the lower end of the address area is also used as a vector area. See 3.3, Interrupts, for details on the vector area. If an odd address is specified as a branch destination or as the operand address of a MOV.W instruction, the least significant bit is regarded as 0, causing word access to be performed at the address preceding the specified address. See 2.3.2, Memory Data Formats, for further information. 2.4.2 Effective Address Calculation Table 2.2 shows how effective addresses are calculated in each of the addressing modes. Arithmetic and logic instructions use register direct addressing (1). The ADD.B, ADDX, SUBX, CMP.B, AND, OR, and XOR instructions can also use immediate addressing (6). Data transfer instructions can use all addressing modes except program-counter relative (7) and memory indirect (8). Bit manipulation instructions use register direct (1), register indirect (2), or 8-bit absolute addressing (5) to specify a byte operand, and 3-bit immediate addressing (6) to specify a bit position in that byte. The BSET, BCLR, BNOT, and BTST instructions can also use register direct addressing (1) to specify the bit position. 20 Table 2.2 No. 1 Effective Address Calculation Effective Address Calculation Method Effective Address (EA) 3 0 3 0 Addressing Mode and Instruction Format Register direct, Rn 15 87 43 0 rm op rm rn rn Operand is contents of registers indicated by rm/rn 15 Contents (16 bits) of register indicated by rm 0 15 0 2 Register indirect, @Rn 15 76 43 0 op 3 rm Register indirect with displacement, @(d:16, Rn) 15 76 43 0 15 Contents (16 bits) of register indicated by rm 0 15 0 op disp 4 rm disp Register indirect with post-increment, @Rn+ 15 76 43 0 15 Contents (16 bits) of register indicated by rm 0 15 0 op rm 1 or 2 Register indirect with pre-decrement, @-Rn 15 76 43 0 15 Contents (16 bits) of register indicated by rm 0 15 0 op rm Incremented or decremented by 1 if operand is byte size, 1 or 2 and by 2 if word size 21 Table 2.2 No. 5 Effective Address Calculation (cont) Effective Address Calculation Method Effective Address (EA) 15 87 0 Addressing Mode and Instruction Format Absolute address @aa:8 15 87 0 H'FF op @aa:16 15 abs 0 15 0 op abs 6 Immediate #xx:8 15 87 0 Operand is 1- or 2-byte immediate data IMM op #xx:16 15 0 op IMM 7 15 0 Program-counter relative @(d:8, PC) PC contents 15 0 15 87 0 Sign extension disp op disp 22 Table 2.2 No. 8 Effective Address Calculation (cont) Effective Address Calculation Method Effective Address (EA) Addressing Mode and Instruction Format Memory indirect, @@aa:8 15 87 0 op abs 15 87 0 H'00 abs 15 0 Memory contents (16 bits) Legend: rm, rn: Register field op: Operation field disp: Displacement IMM: Immediate data abs: Absolute address 23 2.5 Instruction Set The H8/300L Series can use a total of 55 instructions, which are grouped by function in table 2.3. Table 2.3 Function Data transfer Arithmetic operations Logic operations Shift Bit manipulation Branch System control Block data transfer Instruction Set Instructions MOV, PUSH , POP *1 *1 Number 1 14 4 8 14 5 8 1 Total: 55 ADD, SUB, ADDX, SUBX, INC, DEC, ADDS, SUBS, DAA, DAS, MULXU, DIVXU, CMP, NEG AND, OR, XOR, NOT SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR BSET, BCLR, BNOT, BTST, BAND, BIAND, BOR, BIOR, BXOR, BIXOR, BLD, BILD, BST, BIST Bcc*2 , JMP, BSR, JSR, RTS RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP EEPMOV Notes: 1. PUSH Rn is equivalent to MOV.W Rn, @-SP. POP Rn is equivalent to MOV.W @SP+, Rn. The machine language is also the same. 2. Bcc is a conditional branch instruction in which cc represents a condition code. The following sections give a concise summary of the instructions in each category, and indicate the bit patterns of their object code. The notation used is defined next. The functions of the instructions are shown in tables 2.4 to 2.11. The meaning of the operation symbols used in the tables is as follows. 24 Notation Rd Rs Rn (EAd), 25 2.5.1 Data Transfer Instructions Table 2.4 describes the data transfer instructions. Figure 2.5 shows their object code formats. Table 2.4 Instruction MOV Data Transfer Instructions Size* B/W Function (EAs) Rd, Rs (EAd) Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. The Rn, @Rn, @(d:16, Rn), @aa:16, #xx:16, @-Rn, and @Rn+ addressing modes are available for byte or word data. The @aa:8 addressing mode is available for byte data only. The @-R7 and @R7+ modes require word operands. Do not specify byte size for these two modes. POP W @SP+ Rn Pops a 16-bit general register from the stack. Equivalent to MOV.W @SP+, Rn. PUSH W Rn @-SP Pushes a 16-bit general register onto the stack. Equivalent to MOV.W Rn, @-SP. Note: * Size: Operand size B: Byte W: Word Certain precautions are required in data access. See 2.9.1, Notes on Data Access, for details. 26 15 8 7 0 MOV RmRn op 15 8 7 rm rn 0 op 15 8 7 rm rn 0 @RmRn op disp 15 8 7 rm rn @(d:16, Rm)Rn 0 op 15 8 7 rm rn 0 @Rm+Rn, or Rn @-Rm op 15 rn 8 7 abs 0 @aa:8Rn op abs 15 8 7 rn @aa:16Rn 0 op 15 rn 8 7 IMM 0 #xx:8Rn op IMM 15 8 7 rn #xx:16Rn 0 op Legend: op: Operation field rm, rn: Register field disp: Displacement abs: Absolute address IMM: Immediate data 1 1 1 rn PUSH, POP @SP+ Rn, or Rn @-SP Figure 2.5 Data Transfer Instruction Codes 27 2.5.2 Arithmetic Operations Table 2.5 describes the arithmetic instructions. Table 2.5 Instruction ADD SUB Arithmetic Instructions Size* B/W Function Rd Rs Rd, Rd + #IMM Rd Performs addition or subtraction on data in two general registers, or addition on immediate data and data in a general register. Immediate data cannot be subtracted from data in a general register. Word data can be added or subtracted only when both words are in general registers. B Rd Rs C Rd, Rd #IMM C Rd Performs addition or subtraction with carry or borrow on byte data in two general registers, or addition or subtraction on immediate data and data in a general register. B Rd 1 Rd Increments or decrements a general register W Rd 1 Rd, Rd 2 Rd Adds or subtracts immediate data to or from data in a general register. The immediate data must be 1 or 2. B Rd decimal adjust Rd Decimal-adjusts (adjusts to packed 4-bit BCD) an addition or subtraction result in a general register by referring to the CCR B Rd x Rs Rd Performs 8-bit x 8-bit unsigned multiplication on data in two general registers, providing a 16-bit result ADDX SUBX INC DEC ADDS SUBS DAA DAS MULXU DIVXU B Rd / Rs Rd Performs 16-bit / 8-bit unsigned division on data in two general registers, providing an 8-bit quotient and 8-bit remainder CMP B/W Rd - Rs, Rd - #IMM Compares data in a general register with data in another general register or with immediate data, and the result is stored in the CCR. Word data can be compared only between two general registers. NEG B 0 - Rd Rd Obtains the two's complement (arithmetic complement) of data in a general register Note: * Size: Operand size B: Byte W: Word 28 2.5.3 Logic Operations Table 2.6 describes the four instructions that perform logic operations. Table 2.6 Instruction AND Logic Operation Instructions Size* B Function Rd Rs Rd, Rd #IMM Rd Performs a logical AND operation on a general register and another general register or immediate data OR B Rd Rs Rd, Rd #IMM Rd Performs a logical OR operation on a general register and another general register or immediate data XOR B Rd Rs Rd, Rd #IMM Rd Performs a logical exclusive OR operation on a general register and another general register or immediate data NOT B ~ Rd Rd Obtains the one's complement (logical complement) of general register contents Note: * Size: Operand size B: Byte 2.5.4 Shift Operations Table 2.7 describes the eight shift instructions. Table 2.7 Instruction SHAL SHAR SHLL SHLR ROTL ROTR ROTXL ROTXR Note: * Size: Operand size B: Byte B B B Shift Instructions Size* B Function Rd shift Rd Performs an arithmetic shift operation on general register contents Rd shift Rd Performs a logical shift operation on general register contents Rd rotate Rd Rotates general register contents Rd rotate through carry Rd Rotates general register contents through the C (carry) bit 29 Figure 2.6 shows the instruction code format of arithmetic, logic, and shift instructions. 15 8 7 0 op 15 8 7 rm rn 0 ADD, SUB, CMP, ADDX, SUBX (Rm) ADDS, SUBS, INC, DEC, DAA, DAS, NEG, NOT 0 op 15 8 7 rn op 15 8 7 rm rn 0 MULXU, DIVXU op 15 rn 8 7 IMM 0 ADD, ADDX, SUBX, CMP (#XX:8) op 15 8 7 rm rn 0 AND, OR, XOR (Rm) op 15 rn 8 7 IMM 0 AND, OR, XOR (#xx:8) op Legend: op: Operation field rm, rn: Register field IMM: Immediate data rn SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR Figure 2.6 Arithmetic, Logic, and Shift Instruction Codes 30 2.5.5 Bit Manipulations Table 2.8 describes the bit-manipulation instructions. Figure 2.7 shows their object code formats. Table 2.8 Instruction BSET Bit-Manipulation Instructions Size* B Function 1 ( BCLR B 0 ( BNOT B ~ ( BTST B ~ ( BAND B C ( BIAND B C [~ ( BOR B BIOR B C [~ ( Note: * Size: Operand size B: Byte 31 Table 2.8 Instruction BXOR Bit-Manipulation Instructions (cont) Size* B Function C ( BIXOR B C [~( BLD BILD B B BST BIST B B Note: * Size: Operand size B: Byte Certain precautions are required in bit manipulation. See 2.9.2, Notes on Bit Manipulation, for details. 32 BSET, BCLR, BNOT, BTST 15 8 7 0 op 15 8 7 IMM rn 0 Operand: register direct (Rn) Bit No.: immediate (#xx:3) Operand: register direct (Rn) Bit No.: register direct (Rm) 0 op 15 8 7 rm rn op op 15 8 7 rn IMM 0 0 0 0 0 0 0 Operand: register indirect (@Rn) 0 Bit No.: 0 immediate (#xx:3) op op 15 8 7 rn rm 0 0 0 0 0 0 0 Operand: register indirect (@Rn) 0 Bit No.: 0 register direct (Rm) op op 15 8 7 abs IMM 0 0 0 Operand: absolute (@aa:8) 0 Bit No.: 0 immediate (#xx:3) op op rm abs 0 0 0 Operand: absolute (@aa:8) 0 Bit No.: register direct (Rm) BAND, BOR, BXOR, BLD, BST 15 8 7 0 op 15 8 7 IMM rn 0 Operand: register direct (Rn) Bit No.: immediate (#xx:3) op op 15 8 7 rn IMM 0 0 0 0 0 0 0 Operand: register indirect (@Rn) 0 Bit No.: 0 immediate (#xx:3) op op IMM abs 0 0 0 Operand: absolute (@aa:8) 0 Bit No.: immediate (#xx:3) Legend: op: Operation field rm, rn: Register field abs: Absolute address IMM: Immediate data Figure 2.7 Bit Manipulation Instruction Codes 33 BIAND, BIOR, BIXOR, BILD, BIST 15 8 7 0 op 15 8 7 IMM rn 0 Operand: register direct (Rn) Bit No.: immediate (#xx:3) op op 15 8 7 rn IMM 0 0 0 0 0 0 0 Operand: register indirect (@Rn) 0 Bit No.: 0 immediate (#xx:3) op op IMM abs 0 0 0 Operand: absolute (@aa:8) 0 Bit No.: immediate (#xx:3) Legend: op: Operation field rm, rn: Register field abs: Absolute address IMM: Immediate data Figure 2.7 Bit Manipulation Instruction Codes (cont) 34 2.5.6 Branching Instructions Table 2.9 describes the branching instructions. Figure 2.8 shows their object code formats. Table 2.9 Instruction Bcc Branching Instructions Size -- Function Branches to the designated address if the specified condition is true. The branching conditions are given below. Mnemonic BRA (BT) BRN (BF) BHI BLS BCC (BHS) BCS (BLO) BNE BEQ BVC BVS BPL BMI BGE BLT BGT BLE Description Always (true) Never (false) High Low or same Carry clear (high or same) Carry set (low) Not equal Equal Overflow clear Overflow set Plus Minus Greater or equal Less than Greater than Less or equal Condition Always Never CZ=0 CZ=1 C=0 C=1 Z=0 Z=1 V=0 V=1 N=0 N=1 NV=0 NV=1 Z (N V) = 0 Z (N V) = 1 JMP BSR JSR RTS -- -- -- -- Branches unconditionally to a specified address Branches to a subroutine at a specified address Branches to a subroutine at a specified address Returns from a subroutine 35 15 8 7 0 op 15 cc 8 7 disp 0 Bcc op 15 8 7 rm 0 0 0 0 0 JMP (@Rm) op abs 15 8 7 0 JMP (@aa:16) op 15 8 7 abs 0 JMP (@@aa:8) op 15 8 7 disp 0 BSR op 15 8 7 rm 0 0 0 0 0 JSR (@Rm) op abs 15 8 7 0 JSR (@aa:16) op 15 8 7 abs 0 JSR (@@aa:8) op Legend: op: Operation field cc: Condition field rm: Register field disp: Displacement abs: Absolute address RTS Figure 2.8 Branching Instruction Codes 36 2.5.7 System Control Instructions Table 2.10 describes the system control instructions. Figure 2.9 shows their object code formats. Table 2.10 Instruction RTE SLEEP LDC System Control Instructions Size* -- -- B Function Returns from an exception-handling routine Causes a transition from active mode to a power-down mode. See section 5, Power-Down Modes, for details Rs CCR, #IMM CCR Moves immediate data or general register contents to the condition code register STC B CCR Rd Copies the condition code register to a specified general register CCR #IMM CCR Logically ANDs the condition code register with immediate data CCR #IMM CCR Logically ORs the condition code register with immediate data CCR #IMM CCR Logically exclusive-ORs the condition code register with immediate data ANDC B ORC B XORC B NOP -- PC + 2 PC Only increments the program counter Note: * Size: Operand size B: Byte 37 15 8 7 0 op 15 8 7 0 RTE, SLEEP, NOP op 15 8 7 rn 0 LDC, STC (Rn) op IMM ANDC, ORC, XORC, LDC (#xx:8) Legend: op: Operation field rn: Register field IMM: Immediate data Figure 2.9 System Control Instruction Codes 2.5.8 Block Data Transfer Instruction Table 2.11 describes the block data transfer instruction. Figure 2.10 shows its object code format. Table 2.11 Block Data Transfer Instruction Instruction EEPMOV Size -- Function If R4L 0 then repeat @R5+ @R6+, R4L - 1 R4L until else next; Block transfer instruction. Transfers the number of bytes specified by R4L, from locations starting at the address specified by R5, to locations starting at the address specified by R6. On completion of the transfer, the next instruction is executed. R4L = 0 Certain precautions are required in using the EEPMOV instruction. See 2.9.3, Notes on Use of the EEPMOV Instruction, for details. 38 15 8 7 0 op op Legend: op: Operation field Figure 2.10 Block Data Transfer Instruction Code 39 2.6 Basic Operational Timing CPU operation is synchronized by a system clock (o) or a subclock (oSUB). For details on these clock signals see section 4, Clock Pulse Generators. The period from a rising edge of o or oSUB to the next rising edge is called one state. A bus cycle consists of two states or three states. The cycle differs depending on whether access is to on-chip memory or to on-chip peripheral modules. 2.6.1 Access to On-Chip Memory (RAM, ROM) Acess to on-chip memory takes place in two states. The data bus width is 16 bits, allowing access in byte or word size. Figure 2.11 shows the on-chip memory access cycle. Bus cycle T1 state o or o SUB T2 state Internal address bus Address Internal read signal Internal data bus (read access) Read data Internal write signal Internal data bus (write access) Write data Figure 2.11 On-Chip Memory Access Cycle 40 2.6.2 Access to On-Chip Peripheral Modules On-chip peripheral modules are accessed in two states or three states. The data bus width is 8 bits, so access is by byte size only. This means that for accessing word data, two instructions must be used. Two-state access to on-chip peripheral modules Figure 2.12 shows operation timings for accessing on-chip peripheral modules in 2 states. Bus cycle T1 state o or o SUB T2 state Internal address bus Address Internal read signal Internal data bus (read access) Read data Internal write signal Internal data bus (write access) Write data Figure 2.12 On-Chip Peripheral Module Access Cycle (2-State Access) Three-state access to on-chip peripheral modules Figure 2.13 shows operation timings for accessing on-chip peripheral modules in 3 states. 41 Bus cycle T1 state o or o SUB T2 state T3 state Internal address bus Internal read signal Internal data bus (read access) Internal write signal Internal data bus (write access) Address Read data Write data Figure 2.13 On-Chip Peripheral Module Access Cycle (3-State Access) 2.7 2.7.1 CPU States Overview There are four CPU states: the reset state, program execution state, program halt state, and exception-handling state. The program execution state includes active (high-speed or mediumspeed) mode and subactive mode. In the program halt state there are a sleep mode, standby mode, watch mode, and sub-sleep mode. These states are shown in figure 2.14. Figure 2.15 shows the state transitions. 42 CPU state Reset state The CPU is initialized. Program execution state Active (high speed) mode The CPU executes successive program instructions at high speed, synchronized by the system clock Active (medium speed) mode The CPU executes successive program instructions at reduced speed, synchronized by the system clock Subactive mode The CPU executes successive program instructions at reduced speed, synchronized by the subclock Low-power modes Program halt state A state in which some or all of the chip functions are stopped to conserve power Sleep mode Standby mode Watch mode Subsleep mode Exceptionhandling state A transient state in which the CPU changes the processing flow due to a reset or an interrupt exception handling source. Note: See section 5, Power-Down Modes, for details on the modes and their transitions. Figure 2.14 CPU Operation States 43 Reset cleared Reset state Reset occurs Exception-handling state Reset occurs Reset occurs Interrupt source Exception- Exceptionhandling handling request complete Program halt state SLEEP instruction executed Program execution state Figure 2.15 State Transitions 2.7.2 Program Execution State In the program execution state the CPU executes program instructions in sequence. There are three modes in this state, two active modes (high speed and medium speed) and one subactive mode. Operation is synchronized with the system clock in active mode (high speed and medium speed), and with the subclock in subactive mode. See section 5, Power-Down Modes for details on these modes. 2.7.3 Program Halt State In the program halt state there are four modes: sleep mode, standby mode, watch mode, and subsleep mode. See section 5, Power-Down Modes for details on these modes. 2.7.4 Exception-Handling State The exception-handling state is a transient state occurring when exception handling is started by a reset or interrupt and the CPU changes its normal processing flow. In exception handling caused by an interrupt, SP (R7) is referenced and the PC and CCR values are saved on the stack. For details on interrupt handling, see 3.3, Interrupts. 44 2.8 Memory Map Figure 2.16 shows a memory map for the H8/3627 Series. H8/3622 Interrupt vectors (42 bytes) On-chip ROM H8/3623 H8/3624 H8/3625 H8/3626 H8/3627 16 kbytes H'0000 H'0029 H'002A H'3FFF H'5FFF H'7FFF H'9FFF H'BFFF 24 kbytes 32 kbytes 40 kbytes 48 kbytes H'EDFF Reserved H'F77F H'F780 On-chip RAM H'FF7F H'FF80 H'FF8F H'FF90 Reserved Internal I/O registers (112 bytes) H'FFFF Figure 2.16 H8/3627 Series Memory Map 1 kbyte H'EB80 2 kbytes 60 kbytes 45 2.9 2.9.1 Application Notes Notes on Data Access Access to Empty Area: The address space of the H8/300L CPU includes empty areas in addition to the RAM, registers, and ROM areas available to the user. If these empty areas are mistakenly accessed by an application program, the following results will occur. * Data transfer from CPU to empty area: The transferred data will be lost. This action may also cause the CPU to misoperate. * Data transfer from empty area to CPU: Unpredictable data is transferred. Access to the Internal I/O Register: Internal data transfer to or from on-chip modules other than the ROM and RAM areas makes use of an 8-bit data width. If word access is attempted to these areas, the following results will occur. * Word access from CPU to I/O register area: Upper byte: Will be written to I/O register. Lower byte: Transferred data will be lost. * Word access from I/O register to CPU: Upper byte: Will be written to upper part of CPU register. Lower byte: Unpredictable data will be written to lower part of CPU register. Byte size instructions should therefore be used when transferring data to or from I/O registers other than the on-chip ROM and RAM areas. Figure 2.17 shows the data size and number of states in which on-chip peripheral modules can be accessed. 46 Access H8/3622S H8/3623S H8/3624S H8/3625 H8/3626 H8/3627 Word Byte States 24 kbytes 32 kbytes On-chip ROM 40 kbytes H'0029 H'002A H'3FFF H'5FFF H'7FFF H'9FFF H'BFFF Interrupt vectors (42 bytes) 16 kbytes H'0000 48 kbytes 60 kbytes 2 H'EDFF Reserved H'F77F H'F780 2 kbytes -- -- -- On-chip RAM H'FF7F H'FF80 H'FF8F H'FF90 Reserved 1 kbyte H'FB80 2 -- -- -- Internal I/O registers (112 bytes) H'FFFF x 2 or 3 : Access possible x : Not possible Figure 2.17 Data Size and Number of States for Access to and from On-Chip Peripheral Modules 47 2.9.2 Notes on Bit Manipulation The BSET, BCLR, BNOT, BST, and BIST instructions read one byte of data, modify the data, then write the data byte again. Special care is required when using these instructions in cases where two registers are assigned to the same address, in the case of registers that include writeonly bits, and when the instruction accesses an I/O. Order of Operation 1 2 3 Read Modify Write Operation Read byte data at the designated address Modify a designated bit in the read data Write the altered byte data to the designated address Bit Manipulation in Two Registers Assigned to the Same Address Example 1: Bit manipulation to the timer load register and the timer counter Figure 2.18 shows an example in which two timer registers share the same address. When a bit manipulation instruction accesses the timer load register and timer counter of a reloadable timer, since these two registers share the same address, the following operations take place. Order of Operation 1 2 3 Read Modify Write Operation Timer counter data is read (one byte) The CPU modifies (sets or resets) the bit designated in the instruction The altered byte data is written to the timer load register The timer counter is counting, so the value read is not necessarily the same as the value in the timer load register. As a result, bits other than the intended bit in the timer load register may be modified to the timer counter value. R Count clock Timer counter R: Read W: Write W Timer load register Reload Internal bus Figure 2.18 Timer Configuration Example 48 Example 2: Here a BSET instruction is executed designating port 6. P6 7 and P66 are designated as input pins, with a low-level signal input at P67 and a high-level signal at P6 6. The remaining pins, P65 to P60, are output pins and output low-level signals. In this example, the BSET instruction is used to change pin P60 to high-level output. [A: Prior to executing BSET] P67 Input/output Pin state PCR6 PDR6 Input Low level 0 1 P66 Input High level 0 0 P65 Output Low level 1 0 P64 Output Low level 1 0 P63 Output Low level 1 0 P62 Output Low level 1 0 P61 Output Low level 1 0 P60 Output Low level 1 0 [B: BSET instruction executed] BSET #0, @PDR6 The BSET instruction is executed designating port 6. [C: After executing BSET] P67 Input/output Pin state PCR6 PDR6 Input Low level 0 0 P66 Input High level 0 1 P65 Output Low level 1 0 P64 Output Low level 1 0 P63 Output Low level 1 0 P62 Output Low level 1 0 P61 Output Low level 1 0 P60 Output High level 1 1 [D: Explanation of how BSET operates] When the BSET instruction is executed, first the CPU reads port 6. Since P67 and P66 are input pins, the CPU reads the pin states (low-level and high-level input). P6 5 to P60 are output pins, so the CPU reads the value in PDR6. In this example PDR6 has a value of H'80, but the value read by the CPU is H'40. Next, the CPU sets bit 0 of the read data to 1, changing the PDR6 data to H'41. Finally, the CPU writes this value (H'41) to PDR6, completing execution of BSET. As a result of this operation, bit 0 in PDR6 becomes 1, and P6 0 outputs a high-level signal. However, bits 7 and 6 of PDR6 end up with different values. 49 To avoid this problem, store a copy of the PDR6 data in a work area in memory. Perform the bit manipulation on the data in the work area, then write this data to PDR6. [A: Prior to executing BSET] MOV. B MOV. B MOV. B #80, R0L, R0L, P67 Input/output Pin state PCR6 PDR6 RAM0 Input Low level 0 1 1 R0L @RAM0 @PDR6 P66 Input High level 0 0 0 The PDR6 value (H'80) is written to a work area in memory (RAM0) as well as to PDR6. P65 Output Low level 1 0 0 P64 Output Low level 1 0 0 P63 Output Low level 1 0 0 P62 Output Low level 1 0 0 P61 Output Low level 1 0 0 P60 Output Low level 1 0 0 [B: BSET instruction executed] BSET #0, @RAM0 The BSET instruction is executed designating the PDR6 work area (RAM0). [C: After executing BSET] MOV. B MOV. B @RAM0, R0L R0L, @PDR6 P67 Input/output Pin state PCR6 PDR6 RAM0 Input Low level 0 1 1 P66 Input High level 0 0 0 The work area (RAM0) value is written to PDR6. P65 Output Low level 1 0 0 P64 Output Low level 1 0 0 P63 Output Low level 1 0 0 P62 Output Low level 1 0 0 P61 Output Low level 1 0 0 P60 Output High level 1 1 1 50 Bit Manipulation in a Register Containing a Write-only Bit Example 3: In this example, the port 6 control register PCR6 is accessed by a BCLR instruction. As in the examples above, P67 and P66 are input pins, with a low-level signal input at P67 and a high-level signal at P66. The remaining pins, P65 to P60, are output pins that output low-level signals. In this example, the BCLR instruction is used to change pin P60 to an input port. It is assumed that a high-level signal will be input to this input pin. [A: Prior to executing BCLR] P67 Input/output Pin state PCR6 PDR6 Input Low level 0 1 P66 Input High level 0 0 P65 Output Low level 1 0 P64 Output Low level 1 0 P63 Output Low level 1 0 P62 Output Low level 1 0 P61 Output Low level 1 0 P60 Output Low level 1 0 [B: BCLR instruction executed] BCLR #0, @PCR6 The BCLR instruction is executed designating PCR6. [C: After executing BCLR] P67 Input/output Pin state PCR6 PDR6 Output Low level 1 1 P66 Output High level 1 0 P65 Output Low level 1 0 P64 Output Low level 1 0 P63 Output Low level 1 0 P62 Output Low level 1 0 P61 Output Low level 1 0 P60 Input High level 0 0 [D: Explanation of how BCLR operates] When the BCLR instruction is executed, first the CPU reads PCR6. Since PCR6 is a write-only register, the CPU reads a value of H'FF, even though the PCR6 value is actually H'3F. Next, the CPU clears bit 0 in the read data to 0, changing the data to H'FE. Finally, this value (H'FE) is written to PCR6 and BCLR instruction execution ends. As a result of this operation, bit 0 in PCR6 becomes 0, making P6 0 an input port. However, bits 7 and 6 in PCR6 change to 1, so that P6 7 and P66 change from input pins to output pins. 51 To avoid this problem, store a copy of the PCR6 data in a work area in memory. Perform the bit manipulation on the data in the work area, then write this data to PCR6. [A: Prior to executing BCLR] MOV. B MOV. B MOV. B #3F, R0L, R0L, P67 R0L @RAM0 @PCR6 P66 Input High level 0 0 0 The PCR6 value (H'3F) is written to a work area in memory (RAM0) as well as to PCR6. P65 Output Low level 1 0 1 P64 Output Low level 1 0 1 P63 Output Low level 1 0 1 P62 Output Low level 1 0 1 P61 Output Low level 1 0 1 P60 Output Low level 1 0 1 Input/output Pin state PCR6 PDR6 RAM0 Input Low level 0 1 0 [B: BCLR instruction executed] BCLR #0, @RAM0 The BCLR instruction is executed designating the PCR6 work area (RAM0). [C: After executing BCLR] MOV. B MOV. B @RAM0, R0L R0L, @PCR6 P67 Input/output Pin state PCR6 PDR6 RAM0 Input Low level 0 1 0 P66 Input High level 0 0 0 The work area (RAM0) value is written to PCR6. P65 Output Low level 1 0 1 P64 Output Low level 1 0 1 P63 Output Low level 1 0 1 P62 Output Low level 1 0 1 P61 Output Low level 1 0 1 P60 Output High level 0 0 0 52 Table 2.12 lists the registers with shared addresses. Table 2.13 lists the registers that contain writeonly bits. Table 2.12 Registers with Shared Addresses Register Name Port data register 1* Port data register 2* Port data register 5* Port data register 6* Port data register 7* Port data register 8* Port data register A* Abbreviation PDR1 PDR2 PDR5 PDR6 PDR7 PDR8 PDRA Address H'FFD4 H'FFD5 H'FFD8 H'FFD9 H'FFDA H'FFDB H'FFDD Note: * The port data register addresses are also assigned directly to input pins. Table 2.13 Registers with Write-Only Bits Register Name Port control register 1 Port control register 2 Port control register 5 Port control register 6 Port control register 7 Port control register 8 Port control register A Timer control register F Abbreviation PCR1 PCR2 PCR5 PCR6 PCR7 PCR8 PCRA TCRF Address H'FFE4 H'FFE5 H'FFE8 H'FFE9 H'FFEA H'FFEB H'FFED H'FFB6 53 2.9.3 Notes on Use of the EEPMOV Instruction * The EEPMOV instruction is a block data transfer instruction. It moves the number of bytes specified by R4L from the address specified by R5 to the address specified by R6. R5 R6 R5 + R4L R6 + R4L * When setting R4L and R6, make sure that the final destination address (R6 + R4L) does not exceed H'FFFF. The value in R6 must not change from H'FFFF to H'0000 during execution of the instruction. R5 R6 R5 + R4L H'FFFF Not allowed R6 + R4L 54 Section 3 Exception Handling 3.1 Overview Exception handling is performed in the H8/3627 Series when a reset or interrupt occurs. Table 3.1 shows the priorities of these two types of exception handling. Table 3.1 Priority High Exception Handling Types and Priorities Exception Source Reset Interrupt Time of Start of Exception Handling Exception handling starts as soon as the reset state is cleared When an interrupt is requested, exception handling starts after execution of the present instruction or the exception handling in progress is completed Low 3.2 3.2.1 Reset Overview A reset is the highest-priority exception. The internal state of the CPU and the registers of the onchip peripheral modules are initialized. 3.2.2 Reset Sequence As soon as the RES pin goes low, all processing is stopped and the H8/3637 Series enters the reset state. To make sure the chip is reset properly, observe the following precautions. * At power on: Hold the RES pin low until the clock pulse generator output stabilizes. * When an external clock or ceramic oscillator is used, also, at power on the RES pin must be held low for the crystal oscillator oscillation stabilization time shown in table 14.3 in section 14, Electrical Characteristics. * Resetting during operation: Hold the RES pin low for at least 18 system clock cycles. Reset exception handling begins when the RES pin is held low for a given period, then returned to the high level. Reset exception handling takes place as follows. * The CPU internal state and the registers of on-chip peripheral modules are initialized, with the I bit of the condition code register (CCR) set to 1. 55 * The PC is loaded from the reset exception handling vector address (H'0000 to H'0001), after which the program starts executing from the address indicated in PC. When system power is turned on or off, the RES pin should be held low. Figure 3.1 shows the reset sequence. Reset cleared Program initial instruction prefetch Vector fetch Internal processing RES o Internal address bus Internal read signal Internal write signal Internal data bus (16-bit) (1) (2) (2) (3) (1) Reset exception handling vector address (H'0000) (2) Program start address (3) First instruction of program Figure 3.1 Reset Sequence 3.2.3 Interrupt Immediately after Reset After a reset, if an interrupt were to be accepted before the stack pointer (SP: R7) was initialized, PC and CCR would not be pushed onto the stack correctly, resulting in program runaway. To prevent this, immediately after reset exception handling all interrupts are masked. For this reason, the initial program instruction is always executed immediately after a reset. This instruction should initialize the stack pointer (e.g. MOV.W #xx: 16, SP). 56 3.3 3.3.1 Interrupts Overview The interrupt sources include 13 external interrupts (WKP0 to WKP7, IRQ0 to IRQ4), and 16 internal interrupts from on-chip peripheral modules. Table 3.2 shows the interrupt sources, their priorities, and their vector addresses. When more than one interrupt is requested, the interrupt with the highest priority is processed. The interrupts have the following features: * Internal and external interrupts can be masked by the I bit of CCR. When this bit is set to 1, interrupt request flags are set but interrupts are not accepted. * IRQ0 to IRQ4 can each be set independently to either rising edge sensing or falling edge sensing. 57 Table 3.2 Interrupt Sources and Priorities Interrupt Reset IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 WKP 0 WKP 1 WKP 2 WKP 3 WKP 4 WKP 5 WKP 6 WKP 7 SCI1 transfer complete Timer A overflow Timer FL compare match Timer FL overflow Timer FH compare match Timer FH overflow Timer G input capture Timer G overflow SCI3 receive data full SCI3 transmit data empty SCI3 transmit end SCI3 overrun error SCI3 framing error SCI3 parity error 10 11 14 15 16 18 H'0014 to H'0015 H'0016 to H'0017 H'001C to H'001D H'001E to H'001F H'0020 to H'0021 H'0024 to H'0025 Vector Number 0 4 5 6 7 8 9 Vector Address H'0000 to H'0001 H'0008 to H'0009 H'000A to H'000B H'000C to H'000D H'000E to H'000F H'0010 to H'0011 H'0012 to H'0013 Priority High Interrupt Source RES IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 WKP 0 WKP 1 WKP 2 WKP 3 WKP 4 WKP 5 WKP 6 WKP 7 SCI1 Timer A Timer FL Timer FH Timer G SCI3 A/D converter (SLEEP instruction executed) A/D conversion end Direct transfer 19 20 H'0026 to H'0027 H'0028 to H'0029 Low Note: Vector addresses H'0002 to H'0007, H'0018 to H'001B, and H'0022 to H'0023 are reserved and cannot be used. 58 3.3.2 Interrupt Control Registers Table 3.3 lists the registers that control interrupts. Table 3.3 Name Interrupt edge select register Interrupt enable register 1 Interrupt enable register 2 Interrupt request register 1 Interrupt request register 2 Wakeup interrupt request register Interrupt Control Registers Abbreviation IEGR IENR1 IENR2 IRR1 IRR2 IWPR R/W R/W R/W R/W R/W* R/W* R/W* Initial Value H'60 H'00 H'01 H'20 H'01 H'00 Address H'FFF2 H'FFF3 H'FFF4 H'FFF6 H'FFF7 H'FFF9 Note: * Write is enabled only for writing of 0 to clear a flag. Interrupt Edge Select Register (IEGR) Bit 7 -- Initial value Read/Write 0 -- 6 -- 1 -- 5 -- 1 -- 4 IEG4 0 R/W 3 IEG3 0 R/W 2 IEG2 0 R/W 1 IEG1 0 R/W 0 IEG0 0 R/W IEGR is an 8-bit read/write register, used to designate whether pins IRQ0 to IRQ4 are set to rising edge sensing or falling edge sensing. Bit 7--Reserved Bit: Bit 7 is reserved: it is always read as 0, and should be used cleared to 0. Bits 6 and 5--Reserved Bits: Bits 6 and 5 are reserved; they are always read as 1, and cannot be modified. Bit 4--IRQ4 Edge Select (IEG4): Bit 4 selects the input sensing of pin IRQ4/ADTRG. Bit 4: IEG4 0 1 Description Falling edge of IRQ4/ADTRG pin input is detected Rising edge of IRQ4/ADTRG pin input is detected (initial value) 59 Bit 3--IRQ3 Edge Select(IEG3): Bit 3 selects the input sensing of pin IRQ3/TMIF. Bit 3: IEG3 0 1 Description Falling edge of IRQ3/TMIF pin input is detected Rising edge of IRQ3/TMIF pin input is detected (initial value) Bit 2--IRQ2 Edge Select(IEG2): Bit 2 selects the input sensing of pin IRQ2. Bit 2: IEG2 0 1 Description Falling edge of IRQ2 pin input is detected Rising edge of IRQ2 pin input is detected (initial value) Bit 1--IRQ1 Edge Select(IEG1): Bit 1 selects the input sensing of pin IRQ1. Bit 1: IEG1 0 1 Description Falling edge of IRQ1 pin input is detected Rising edge of IRQ1 pin input is detected (initial value) Bit 0--IRQ0 Edge Select(IEG0): Bit 0 selects the input sensing of pin IRQ0. Bit 0: IEG0 0 1 Description Falling edge of IRQ0 pin input is detected Rising edge of IRQ0 pin input is detected (initial value) 60 Interrupt Enable Register 1 (IENR1) IENR1 is an 8-bit read/write register that enables or disables interrupt requests. Bit 7 IENTA Initial value Read/Write 0 R/W 6 IENS1 0 R/W 5 IENWP 0 R/W 4 IEN4 0 R/W 3 IEN3 0 R/W 2 IEN2 0 R/W 1 IEN1 0 R/W 0 IEN0 0 R/W Bit 7--Timer A Interrupt Enable (IENTA): Bit 7 enables or disables timer A overflow interrupt requests. Bit 7: IENTA 0 1 Description Disables timer A interrupts Enables timer A interrupts (initial value) Bit 6--SCI1 Interrupt Enable (IENS1): Bit 6 enables or disables SCI1 transfer complete interrupt requests. Bit 6: IENS1 0 1 Description Disables SCI1 interrupts Enables SCI1 interrupts (initial value) Bit 5--Wakeup Interrupt Enable (IENWP): Bit 5 enables or disables WKP7 to WKP0 interrupt requests. Bit 5: IENWP 0 1 Description Disables interrupt requests from WKP 7 to WKP 0 Enables interrupt requests from WKP 7 to WKP 0 (initial value) Bits 4 to 0: IRQ4 to IRQ0 Interrupt Enable (IEN4 to IEN0): Bits 4 to 0 enable or disable IRQ4 to IRQ0 interrupt requests. Bits 4 to 0: IEN4 to IEN0 0 1 Description Disables interrupt requests from IRQ4 to IRQ0 Enables interrupt requests from IRQ4 to IRQ0 (initial value) 61 Interrupt Enable Register 2 (IENR2) Bit 7 IENDT Initial value Read/Write 0 R/W 6 IENAD 0 R/W 5 -- 0 -- 4 IENTG 0 R/W 3 IENTFH 0 R/W 2 IENTFL 0 R/W 1 -- 0 -- 0 -- 1 -- IENR2 is an 8-bit read/write register that enables or disables interrupt requests. Bit 7--Direct Transfer Interrupt Enable (IENDT): Bit 7 enables or disables direct transfer interrupt requests. Bit 7: IENDT 0 1 Description Disables direct transfer interrupt requests Enables direct transfer interrupt requests (initial value) Bit 6--A/D Converter Interrupt Enable (IENAD): Bit 6 enables or disables A/D converter end interrupt requests. Bit 6: IENAD 0 1 Description Disables A/D converter interrupt requests Enables A/D converter interrupt requests (initial value) Bit 5--Reserved Bit: Bit 5 is reserved: it is always read as 0, and should be used cleared to 0. Bit 4--Timer G Interrupt Enable (IENTG): Bit 4 enables or disables timer G input capture and overflow interrupt requests. Bit 4: IENTG 0 1 Description Disables timer G interrupts Enables timer G interrupts (initial value) Bit 3--Timer FH Interrupt Enable (IENTFH): Bit 3 enables or disables timer FH compare match and overflow interrupt requests. Bit 3: IENTFH 0 1 Description Disables timer FH interrupts Enables timer FH interrupts (initial value) 62 Bit 2--Timer FL Interrupt Enable (IENTFL): Bit 2 enables or disables timer FL compare match and overflow interrupt requests. Bit 2: IENTFL 0 1 Description Disables timer FL interrupts Enables timer FL interrupts (initial value) Bit 1--Reserved Bit: Bit 1 is reserved: it is always read as 0, and should be used cleared to 0. Bit 0--Reserved Bit: Bit 0 is reserved: it is always read as 1, and cannot be modified. For details of SCI3 interrupt control, see Serial Control Register 3 (SCR3), in section 10.3.2. Interrupt Request Register 1 (IRR1) Bit 7 IRRTA Initial value Read/Write 0 R/W* 6 IRRS1 0 R/W* 5 -- 1 -- 4 IRRI4 0 R/W* 3 IRRI3 0 R/W* 2 IRRI2 0 R/W* 1 IRRI1 0 R/W* 0 IRRI0 0 R/W* Note: * Only a write of 0 for flag clearing is possible. IRR1 is an 8-bit read/write register, in which the corresponding bit is set to 1 when a timer A, SCI1, or IRQ 4 to IRQ0 interrupt is requested. The flags are not cleared automatically when an interrupt is accepted. It is necessary to write 0 to clear each flag. Bit 7--Timer A Interrupt Request Flag (IRRTA) Bit 7: IRRTA 0 1 Description [Clearing conditions] When IRRTA = 1, it is cleared by writing 0 (initial value) [Setting conditions] When the timer A counter value overflows (goes from H'FF to H'00) Bit 6--SCI1 Interrupt Request Flag (IRRS1) Bit 6: IRRS1 0 1 Description [Clearing conditions] When IRRS1 = 1, it is cleared by writing 0 [Setting conditions] When an SCI1 transfer is completed 63 (initial value) Bit 5--Reserved Bit: Bit 5 is reserved; it is always read as 1, and cannot be modified. Bits 4 to 0--IRQ4 to IRQ0 Interrupt Request Flags (IRRI4 to IRRI0) Bits 4 to 0: IRRI4 to IRRI0 0 1 Description [Clearing conditions] When IRRIn = 1, it is cleared by writing 0 to IRRIn. (initial value) [Setting conditions] IRRIn is set when pin IRQn is set to interrupt input, and the designated signal edge is detected. (n = 4 to 0) Interrupt Request Register 2 (IRR2) Bit 7 IRRDT Initial value Read/Write 0 R/W* 6 IRRAD 0 R/W* 5 -- 0 -- 4 IRRTG 0 R/W* 3 IRRTFH 0 R/W* 2 IRRTFL 0 R/W* 1 -- 0 -- 0 -- 1 -- Note: * Only a write of 0 for flag clearing is possible. IRR2 is an 8-bit register containing direct transfer, A/D converter, timer G, timer FH, and timer FL, interrupt flags. When a direct transfer, A/D converter, timer G, timer FH, or timer FL, interrupt is requested, the corresponding flag is set to 1. The flags are not cleared automatically when an interrupt is accepted. It is necessary to write 0 to clear each flag. Bit 7--Direct Transfer Interrupt Request Flag (IRRDT) Bit 7: IRRDT 0 1 Description [Clearing conditions] When IRRDT = 1, it is cleared by writing 0 (initial value) [Setting conditions] When DTON = 1 and a direct transfer is made immediately after a SLEEP instruction is executed 64 Bit 6--A/D Converter Interrupt Request Flag (IRRAD) Bit 6: IRRAD 0 1 Description [Clearing conditions] When IRRAD = 1, it is cleared by writing 0 [Setting conditions] When A/D conversion is completed and ADSF is reset (initial value) Bit 5--Reserved Bit: Bit 5 is reserved: it is always read as 0, and should be used cleared to 0. Bit 4--Timer G Interrupt Request Flag (IRRTG) Bit 4: IRRTG 0 1 Description [Clearing conditions] When IRRTG = 1, it is cleared by writing 0 (initial value) [Setting conditions] When pin TMIG is set to TMIG input and the designated signal edge is detected, or when TCG overflows (from H'FF to H'00) while TMG OVIE is set to 1 Bit 3--Timer FH Interrupt Request Flag (IRRTFH) Bit 3: IRRTFH 0 1 Description [Clearing conditions] When IRRTFH = 1, it is cleared by writing 0 (initial value) [Setting conditions] When counter FH matches output compare register FH in 8-bit timer mode, or when 16-bit counter F (TCFL, TCFH) matches output compare register F (OCRFL, OCRFH) in 16-bit timer mode Bit 2--Timer FL Interrupt Request Flag (IRRTFL) Bit 2: IRRTFL 0 1 Description [Clearing conditions] When IRRTFL = 1, it is cleared by writing 0 (initial value) [Setting conditions] When counter FL matches output compare register FL in 8-bit timer mode Bit 1--Reserved Bit: Bit 1 is reserved: it is a always read as 0, and should be used cleared to 0. Bit 0--Reserved Bit: Bit 0 is reserved: it is a always read as 1, and cannot be modified. 65 Wakeup Interrupt Request Register (IWPR) Bit 7 IWPF7 Initial value Read/Write 0 R/W* 6 IWPF6 0 R/W* 5 IWPF5 0 R/W* 4 IWPF4 0 R/W* 3 IWPF3 0 R/W* 2 IWPF2 0 R/W* 1 IWPF1 0 R/W* 0 IWPF0 0 R/W* Note: * Only a write of 0 for flag clearing is possible. IWPR is an 8-bit read/write register, in which the corresponding bit is set to 1 when pins WKP7 to WKP0 are set to wakeup input and a pin receives a falling edge input. The flags are not cleared automatically when an interrupt is accepted. It is necessary to write 0 to clear each flag. Bits 7 to 0--Wakeup Interrupt Request Flags (IWPF7 to IWPF0) Bits 7 to 0: IWPF7 to IWPF0 0 1 Description [Clearing conditions] When IWPFn = 1, it is cleared by writing 0 to IWPFn. (initial value) [Setting conditions] IWPFn is set when pin WKP n is set to wakeup interrupt input, and a falling edge input is detected at the pin. (n = 7 to 0) 66 3.3.3 External Interrupts There are 13 external interrupts, WKP0 to WKP7 and IRQ 0 to IRQ4. Interrupts WKP0 to WKP7: Interrupts WKP 0 to WKP7 are requested by falling edge inputs at pins WKP0 to WKP7. When these pins are designated as WKP0 to WKP7 pins in port mode register 5 (PMR5) and falling edge input is detected, the corresponding bit in the wakeup interrupt request register (IWPR) is set to 1, requesting an interrupt. Wakeup interrupt requests can be disabled by clearing the IENWP bit in IENR1 to 0. It is also possible to mask all interrupts by setting the CCR I bit to 1. When an interrupt exception handling request is received for interrupts WKP0 to WKP7, the CCR I bit is set to 1. The vector number for interrupts WKP0 to WKP7 is 9. Since all eight interrupts are assigned the same vector number, the interrupt source must be determined by the exception handling routine. Interrupts IRQ0 to IRQ4: Interrupts IRQ 0 to IRQ4 are requested by inputs into pins IRQ0 to IRQ4. These interrupts are detected by either rising edge sensing or falling edge sensing, depending on the settings of bits IEG0 to IEG4 in the edge select register (IEGR). When these pins are designated as pins IRQ0 to IRQ4 in port mode registers 1 and 2 (PMR1 and PMR2) and the designated edge is input, the corresponding bit in IRR1 is set to 1, requesting an interrupt. Interrupts IRQ0 to IRQ4 can be disabled by clearing bits IEN0 to IEN4 in IENR1 to 0. All interrupts can be masked by setting the I bit in CCR to 1. When IRQ 0 to IRQ4 interrupt exception handling is initiated, the I bit in CCR is set to 1. Vector numbers 4 to 8 are assigned to interrupts IRQ0 to IRQ4. The order of priority is from IRQ0 (high) to IRQ4 (low). Table 3.2 gives details. 3.3.4 Internal Interrupts There are 16 internal interrupts that can be requested by the on-chip peripheral modules. When a peripheral module requests an interrupt, the corresponding bit in IRR1 or IRR2 is set to 1. Individual interrupt requests can be disabled by clearing the corresponding bit in IENR1 or IENR2 to 0. All interrupts can be masked by setting the I bit in CCR to 1. When an internal interrupt request is accepted, the I bit in CCR is set to 1. Vector numbers 10 to 20 are assigned to these interrupts. Table 3.2 shows the order of priority of interrupts from on-chip peripheral modules. 67 3.3.5 Interrupt Operations Interrupts are controlled by an interrupt controller. Figure 3.2 shows a block diagram of the interrupt controller. Figure 3.3 shows the flow up to interrupt acceptance. Interrupt controller External or internal interrupts Priority decision logic Interrupt request External interrupts or internal interrupt enable signals I CCR (CPU) Figure 3.2 Block Diagram of Interrupt Controller 68 Interrupt operation is described as follows. 1. When an interrupt condition is met while the interrupt enable register bit is set to 1, an interrupt request signal is sent to the interrupt controller. 2. When the interrupt controller receives an interrupt request, it sets the interrupt request flag. 3. From among the interrupts with interrupt request flags set to 1, the interrupt controller selects the interrupt request with the highest priority and holds the others pending. (Refer to table 3.2 for a list of interrupt priorities.) 4. The interrupt controller checks the I bit of CCR. If the I bit is 0, the selected interrupt request is accepted; if the I bit is 1, the interrupt request is held pending. 5. If the interrupt is accepted, after processing of the current instruction is completed, both PC and CCR are pushed onto the stack. The state of the stack at this time is shown in figure 3.4. The PC value pushed onto the stack is the address of the first instruction to be executed upon return from interrupt handling. 6. The I bit of CCR is set to 1, masking all further interrupts. 7. The vector address corresponding to the accepted interrupt is generated, and the interrupt handling routine located at the address indicated by the contents of the vector address is executed. Notes: 1. When disabling interrupts by clearing bits in an interrupt enable register, or when clearing bits in an interrupt request register, always do so while interrupts are masked (I = 1). 2. If the above clear operations are performed while I = 0, and as a result a conflict arises between the clear instruction and an interrupt request, exception processing for the interrupt will be executed after the clear instruction has been executed. 69 Program execution state IRRI0 = 1 Yes IEN0 = 1 Yes No No No IRRI1 = 1 Yes IEN1 = 1 Yes No No IRRI2 = 1 Yes IEN2 = 1 Yes No IRRDT = 1 Yes IENDT = 1 Yes No No No I=0 Yes PC contents saved CCR contents saved I1 Branch to interrupt handling routine Legend: PC: Program counter CCR: Condition code register I bit of CCR I: Figure 3.3 Flow up to Interrupt Acceptance 70 SP - 4 SP - 3 SP - 2 SP - 1 SP (R7) Stack area SP (R7) SP + 1 SP + 2 SP + 3 SP + 4 CCR CCR* PCH PCL Even address Prior to start of interrupt exception handling Legend: PCH: Upper 8 bits of program counter (PC) PCL: Lower 8 bits of program counter (PC) CCR: Condition code register SP: Stack pointer PC and CCR saved to stack After completion of interrupt exception handling Notes: 1. PC shows the address of the first instruction to be executed upon return from the interrupt handling routine. 2. Register contents must always be saved and restored by word access, starting from an even-numbered address. * Ignored on return from interrupt. Figure 3.4 Stack State after Completion of Interrupt Exception Handling Figure 3.5 shows a typical interrupt sequence where the program area is in the on-chip ROM and the stack area is in the on-chip RAM. 71 72 Interrupt is accepted Instruction prefetch Internal processing Stack access Vector fetch Prefetch instruction of Internal interrupt-handling routine processing (1) (3) (5) (6) (8) (9) (2) (4) (1) (7) (9) (10) Interrupt level decision and wait for end of instruction Interrupt request signal o Internal address bus Internal read signal Figure 3.5 Interrupt Sequence Internal write signal Internal data bus (16 bits) (1) Instruction prefetch address (Instruction is not executed. Address is saved as PC contents, becoming return address.) (2)(4) Instruction code (not executed) (3) Instruction prefetch address (Instruction is not executed.) (5) SP - 2 (6) SP - 4 (7) CCR (8) Vector address (9) Starting address of interrupt-handling routine (contents of vector) (10) First instruction of interrupt-handling routine 3.3.6 Interrupt Response Time Table 3.4 shows the number of wait states after an interrupt request flag is set until the first instruction of the interrupt handler is executed. Table 3.4 Item Waiting time for completion of executing instruction* Saving of PC and CCR to stack Vector fetch Instruction fetch Internal processing Note: * Not including EEPMOV instruction. Interrupt Wait States States 1 to 13 4 2 4 4 Total 15 to 27 73 3.4 3.4.1 Application Notes Notes on Stack Area Use When word data is accessed in the H8/3637 Series, the least significant bit of the address is regarded as 0. Access to the stack always takes place in word size, so the stack pointer (SP: R7) should never indicate an odd address. Use PUSH Rn (MOV.W Rn, @-SP) or POP Rn (MOV.W @SP+, Rn) to save or restore register values. Setting an odd address in SP may cause a program to crash. An example is shown in figure 3.6. SP SP PCH PC L SP R1L PC L H'FEFC H'FEFD H'FEFF BSR instruction SP set to H'FEFF MOV. B R1L, @-R7 Contents of PCH are lost Stack accessed beyond SP Legend: PCH: Upper byte of program counter PCL: Lower byte of program counter R1L: General register R1L SP: Stack pointer Figure 3.6 Operation when Odd Address is Set in SP When CCR contents are saved to the stack during interrupt exception handling or restored when RTE is executed, this also takes place in word size. Both the upper and lower bytes of word data are saved to the stack; on return, the even address contents are restored to CCR while the odd address contents are ignored. 3.4.2 Notes on Rewriting Port Mode Registers When a port mode register is rewritten to switch the functions of external interrupt pins, the following points should be observed. 74 When an external interrupt pin function is switched by rewriting the port mode register that controls these pins (IRQ4 to IRQ0, and WKP7 to WKP0), the interrupt request flag may be set to 1 at the time the pin function is switched, even if no valid interrupt is input at the pin. Be sure to clear the interrupt request flag to 0 after switching pin functions. Table 3.5 shows the conditions under which interrupt request flags are set to 1 in this way. Table 3.5 Conditions under which Interrupt Request Flag is Set to 1 Conditions * * IRRI3 * * IRRI2 * * IRRI1 * * IRRI0 * * IWPR IWPF7 IWPF6 IWPF5 IWPF4 IWPF3 IWPF2 IWPF1 IWPF0 When PMR2 bit IRQ4 is changed from 0 to 1 while pin IRQ4 is low and IEGR bit IEG4 = 0. When PMR2 bit IRQ4 is changed from 1 to 0 while pin IRQ4 is low and IEGR bit IEG4 = 1. When PMR1 bit IRQ3 is changed from 0 to 1 while pin IRQ3 is low and IEGR bit IEG3 = 0. When PMR1 bit IRQ3 is changed from 1 to 0 while pin IRQ3 is low and IEGR bit IEG3 = 1. When PMR1 bit IRQ2 is changed from 0 to 1 while pin IRQ2 is low and IEGR bit IEG2 = 0. When PMR1 bit IRQ2 is changed from 1 to 0 while pin IRQ2 is low and IEGR bit IEG2 = 1. When PMR1 bit IRQ1 is changed from 0 to 1 while pin IRQ1 is low and IEGR bit IEG1 = 0. When PMR1 bit IRQ1 is changed from 1 to 0 while pin IRQ1 is low and IEGR bit IEG1 = 1. When PMR2 bit IRQ0 is changed from 0 to 1 while pin IRQ0 is low and IEGR bit IEG0 = 0. When PMR2 bit IRQ0 is changed from 1 to 0 while pin IRQ0 is low and IEGR bit IEG0 = 1. Interrupt Request Flags Set to 1 IRR1 IRRI4 When PMR5 bit WKP7 is changed from 0 to 1 while pin WKP 7 is low When PMR5 bit WKP6 is changed from 0 to 1 while pin WKP 6 is low When PMR5 bit WKP5 is changed from 0 to 1 while pin WKP 5 is low When PMR5 bit WKP4 is changed from 0 to 1 while pin WKP 4 is low When PMR5 bit WKP3 is changed from 0 to 1 while pin WKP 3 is low When PMR5 bit WKP2 is changed from 0 to 1 while pin WKP 2 is low When PMR5 bit WKP1 is changed from 0 to 1 while pin WKP 1 is low When PMR5 bit WKP0 is changed from 0 to 1 while pin WKP 0 is low 75 Figure 3.7 shows the procedure for setting a bit in a port mode register and clearing the interrupt request flag. When switching a pin function, mask the interrupt before setting the bit in the port mode register. After accessing the port mode register, execute at least one instruction (e.g., NOP), then clear the interrupt request flag from 1 to 0. If the instruction to clear the flag is executed immediately after the port mode register access without executing an intervening instruction, the flag will not be cleared. An alternative method is to avoid the setting of interrupt request flags when pin functions are switched by keeping the pins at the high level so that the conditions in table 3.5 do not occur. Interrupts masked. (Another possibility is to disable the relevant interrupt in interrupt enable register 1.) CCR I bit 1 Set port mode register bit Execute NOP instruction Clear interrupt request flag to 0 After setting the port mode register bit, first execute at least one instruction (e.g., NOP), then clear the interrupt request flag to 0 CCR I bit 0 Interrupt mask cleared Figure 3.7 Port Mode Register Setting and Interrupt Request Flag Clearing Procedure 76 Section 4 Clock Pulse Generators 4.1 Overview Clock oscillator circuitry (CPG: clock pulse generator) is provided on-chip, including both a system clock pulse generator and a subclock pulse generator. The system clock pulse generator consists of a system clock oscillator and system clock dividers. The subclock pulse generator consists of a subclock oscillator circuit and a subclock divider. 4.1.1 Block Diagram Figure 4.1 shows a block diagram of the clock pulse generators. o OSC o Prescaler S (13 bits) oW /2 oW /4 oW /8 o/2 to o/8192 oW oSUB o W /2 o W /4 o W /8 to o W /128 OSC 1 OSC 2 System clock oscillator o OSC (f OSC) oOSC/2 System clock divider (1/2) System clock oOSC/16 divider (1/8) System clock pulse generator X1 X2 Subclock oscillator oW (f W ) Subclock divider (1/2, 1/4, 1/8) Subclock pulse generator Prescaler W (5 bits) Figure 4.1 Block Diagram of Clock Pulse Generators 4.1.2 System Clock and Subclock The basic clock signals that drive the CPU and on-chip peripheral modules are o and oSUB. Four of the clock signals have names: o is the system clock, oSUB is the subclock, oOSC is the oscillator clock, and o W is the watch clock. The clock signals available for use by peripheral modules are oOSC , o/2, o/4, o/8, o/16, o/32, o/64, o/128, o/256, o/512, o/1024, o/2048, o/4096, o/8192, oW, oW /2, oW /4, oW /8, oW /16, oW /32, oW /64, and oW /128. The clock requirements differ from one module to another. 77 4.2 System Clock Generator Clock pulse can be supplied to the system clock divider either by connecting a crystal or ceramic oscillator, or by providing external clock input. Connecting a Crystal Oscillator: Figure 4.2 shows a typical method of connecting a crystal oscillator. C1 OSC 1 Rf OSC 2 C2 R f = 1 M 20% C1 = C 2 = 12 pF 20% Figure 4.2 Typical Connection to Crystal Oscillator Figure 4.3 shows the equivalent circuit of a crystal oscillator. An oscillator having the characteristics given in table 4.1 should be used. CS LS OSC 1 RS OSC 2 C0 Figure 4.3 Equivalent Circuit of Crystal Oscillator Table 4.1 Frequency RS (max) C0 (max) Crystal Oscillator Parameters 2 MHz 500 7 pF 4 MHz 100 7 pF 8 MHz 50 7 pF 10 MHz 30 7 pF 78 Connecting a Ceramic Oscillator: Figure 4.4 shows a typical method of connecting a ceramic oscillator. C1 OSC 1 Rf OSC 2 C2 Rf = 1 M 20% C1 = 30 pF 10% C2 = 30 pF 10% Ceramic oscillator: Murata Figure 4.4 Typical Connection to Ceramic Oscillator Notes on Board Design: When generating clock pulses by connecting a crystal or ceramic oscillator, pay careful attention to the following points. Avoid running signal lines close to the oscillator circuit, since the oscillator may be adversely affected by induction currents. (See figure 4.5.) The board should be designed so that the oscillator and load capacitors are located as close as possible to pins OSC1 and OSC2. To be avoided Signal A Signal B C1 OSC 1 OSC 2 C2 Figure 4.5 Board Design of Oscillator Circuit 79 External Clock Input Method: Connect an external clock signal to pin OSC1, and leave pin OSC2 open. Figure 4.6 shows a typical connection. OSC 1 OSC 2 External clock input Open Figure 4.6 External Clock Input (Example) Frequency Duty cycle Oscillator Clock (oOSC) 45% to 55% 80 4.3 Subclock Generator Connecting a 32.768-kHz Crystal Oscillator: Clock pulses can be supplied to the subclock divider by connecting a 32.768-kHz crystal oscillator, as shown in figure 4.7. Follow the same precautions as noted in 4.2, Notes on Board Design. C1 X1 X2 C2 C1 = C 2 = 15 pF (typ.) Figure 4.7 Typical Connection to 32.768-kHz Crystal Oscillator Figure 4.8 shows the equivalent circuit of the 32.768-kHz crystal oscillator. CS LS X1 RS X2 C0 C0 = 1.5 pF typ RS = 14 k typ f W = 32.768 kHz Crystal oscillator: MX38T (Nihon Denpa Kogyo) Figure 4.8 Equivalent Circuit of 32.768-kHz Crystal Oscillator Pin Connection when Not Using Subclock: When the subclock is not used, connect pin X1 to VCC and leave pin X2 open, as shown in figure 4.9. VCC X1 X2 Open Figure 4.9 Pin Connection when not Using Subclock 81 4.4 Prescalers The H8/3637 Series is equipped with two on-chip prescalers having different input clocks (prescaler S and prescaler W). Prescaler S is a 13-bit counter using the system clock (o) as its input clock. Its prescaled outputs provide internal clock signals for on-chip peripheral modules. Prescaler W is a 5-bit counter using a 32.768-kHz signal divided by 4 (oW/4) as its input clock. Its prescaled outputs are used by timer A as a time base for timekeeping. Prescaler S (PSS): Prescaler S is a 13-bit counter using the system clock (o) as its input clock. It is incremented once per clock period. Prescaler S is initialized to H'0000 by a reset, and starts counting on exit from the reset state. In standby mode, watch mode, subactive mode, and subsleep mode, the system clock pulse generator stops. Prescaler S also stops and is initialized to H'0000. The CPU cannot read or write prescaler S. The output from prescaler S is shared by the on-chip peripheral modules. The divider ratio can be set separately for each on-chip peripheral function. In active (medium-speed) mode the clock input to prescaler S is oOSC /16. Prescaler W (PSW): Prescaler W is a 5-bit counter using a 32.768 kHz signal divided by 4 (oW /4) as its input clock. Prescaler W is initialized to H'00 by a reset, and starts counting on exit from the reset state. Even in standby mode, watch mode, subactive mode, or subsleep mode, prescaler W continues functioning so long as clock signals are supplied to pins X1 and X2. Prescaler W can be reset by setting 1s in bits TMA3 and TMA2 of timer mode register A (TMA). Output from prescaler W can be used to drive timer A, in which case timer A functions as a time base for timekeeping. 4.5 Note on Oscillators Oscillator characteristics of both the masked ROM and ZTATTM versions are closely related to board design and should be carefully evaluated by the user, referring to the examples shown in this section and figure 4.10, Example of Crystal and Ceramic Oscillator Layout. Oscillator circuit constants will differ depending on the oscillator element, stray capacitance in its interconnecting circuit, and other factors. Suitable constants should be determined in consultation with the oscillator element manufacturer. Design the circuit so that the oscillator element never receives voltages exceeding its maximum rating. 82 CVCC X1 X2 VSS OSC2 OSC1 TEST (VSS) Figure 4.10 Example of Crystal and Ceramic Oscillator Layout. 83 84 Section 5 Power-Down Modes 5.1 Overview The H8/3627 Series has seven modes of operation after a reset. These include six power-down modes, in which power dissipation is significantly reduced. Table 5.1 gives a summary of the seven operation modes. Table 5.1 Operation Modes Description The CPU runs on the system clock, executing program instructions at high speed The CPU runs on the system clock, executing program instructions at reduced speed The CPU runs on the subclock, executing program instructions at reduced speed The CPU halts. On-chip peripheral modules continue to operate on the system clock. The CPU halts. Timer A, and timer G, continue to operate on the subclock. The CPU halts. The time-base function of Timer A continues to operate on the subclock. The CPU and all on-chip peripheral modules stop operating Operating Mode Active (high-speed) mode Active (medium-speed) mode Subactive mode Sleep mode Subsleep mode Watch mode Standby mode All but the active (high-speed) mode are power-down modes. In this section the two active modes (high-speed and medium-speed) are referred to collectively as active mode. Figure 5.1 shows the transitions among these operation modes. Table 5.2 indicates the internal states in each mode. 85 Program executing Reset state LSON = 0, MSON = 0 Program execution stopped tio n in s tru c Program execution stopped Active (high-speed) mode *1 P ion EE uct SL str in SL EE P EE io n SL EE P ru ct LSON = 0, MSON = 1 Active (medium-speed) mode D *4 *1 SSBY = 1, TMA3 = 1 D TO N = 1 Watch mode S E LE P in u str cti on = 1 D TO N in s in st TO tru P N = *3 ct io n Standby mode SL in s tru c tio n SSBY = 1, TMA3 = 0, LSON = 0 SL EE P *4 *3 SSBY = 0, LSON = 0 1 Sleep mode SL *1 EE P in LSON = 1, TMA3 = 1 ct io st ru SLEEP instruction *2 SSBY = 0, LSON = 1, TMA3 = 1 n Subactive mode Subsleep mode : Transition caused by exception handling Power-down mode A transition between different modes cannot be made to occur simply because an interrupt request is generated. Make sure that the interrupt is accepted and interrupt handling is performed. Details on the mode transition conditions are given in the explanations of each mode, in sections 5.2 through 5.8. Notes: 1. Timer A interrupt, IRQ 0 interrupt, WKP0 to WKP7 interrupts 2. Timer A interrupt, timer G interrupt, IRQ0 to IRQ4 interrupts, WKP0 to WKP7 interrupts 3. All interrupts 4. IRQ 0 interrupt, IRQ 1 interrupt, WKP0 to WKP7 interrupts Figure 5.1 Operation Mode Transition Diagram 86 Table 5.2 Internal State in Each Operation Mode Active Mode Function System clock oscillator Subclock oscillator CPU operation High Speed Medium Speed Sleep Mode Watch Mode Subactive Subsleep Mode Mode Stopped Functional Functional Stopped Functional Stopped Retained Standby Mode Stopped Functional Stopped Retained Retained*1 Functional Functional Functional Stopped Functional Functional Functional Functional Stopped Retained Instructions Functional Functional Stopped RAM Registers I/O Retained External interrupts IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 WKP0 WKP1 WKP2 WKP3 WKP4 WKP5 WKP6 WKP7 Functional Functional Functional Functional Retained*4 Functional Functional Functional Retained*4 Functional Functional Functional Functional Functional Functional Functional Peripheral module functions Timer A Timer F Timer G SCI1 SCI3 DTMF A/D Functional Functional Functional Functional*3 Functional*3 Functional*3 Retained Retained Retained Retained Functional/ Functional/ Retained*2 Retained*2 Functional Functional Functional Retained Reset Functional Functional Functional Reset Functional Functional Functional Retained Retained Reset Reset Retained Retained Reset Reset Retained Retained Reset Reset Retained Notes: 1. 2. 3. 4. Register contents held; high-impedance output. Functional only if oW/2 internal clock is selected; otherwise stopped and retained. Functional when timekeeping time-base function is selected. External interrupt requests are ignored. The interrupt request register contents are not affected. 87 5.1.1 System Control Registers The operation mode is selected using the system control registers described in table 5.3. Table 5.3 Name System control register 1 System control register 2 System Control Register Abbreviation SYSCR1 SYSCR2 R/W R/W R/W Initial Value H'07 H'E0 Address H'FFF0 H'FFF1 System Control Register 1 (SYSCR1) Bit 7 SSBY Initial value Read/Write 0 R/W 6 STS2 0 R/W 5 STS1 0 R/W 4 STS0 0 R/W 3 LSON 0 R/W 2 -- 1 -- 1 -- 1 -- 0 -- 1 -- SYSCR1 is an 8-bit read/write register for control of the power-down modes. Upon reset, SYSCR1 is initialized to H'07. Bit 7--Software Standby (SSBY): This bit designates transition to standby mode or watch mode. Bit 7: SSBY 0 Description * * 1 * * When a SLEEP instruction is executed in active mode, a transition is made to sleep mode. When a SLEEP instruction is executed in subactive mode, a transition is made to subsleep mode. (initial value) When a SLEEP instruction is executed in active mode, a transition is made to standby mode or watch mode. When a SLEEP instruction is executed in subactive mode, a transition is made to watch mode. Bits 6 to 4--Standby Timer Select 2 to 0 (STS2 to STS0): These bits designate the time the CPU and peripheral modules wait for stable clock operation after exiting from standby mode or watch mode to active mode due to an interrupt. The designation should be made according to the clock frequency so that the waiting time is at least 10 ms. 88 Bit 6: STS2 0 Bit 5: STS1 0 Bit 4: STS0 0 1 Description Wait time = 8,192 states Wait time = 16,384 states Wait time = 32,768 states Wait time = 65,536 states Wait time = 131,072 states (initial value) 1 0 1 1 * * Note: * Don't care Bit 3--Low Speed on Flag (LSON): This bit chooses the system clock (o) or subclock (oSUB ) as the CPU operating clock when watch mode is cleared. The resulting operation mode depends on the combination of other control bits and interrupt input. Bit 3: LSON 0 1 Description The CPU operates on the system clock (o) The CPU operates on the subclock (o SUB) (initial value) Bits 2 to 0--Reserved Bits: These bits are reserved; they are always read as 1, and cannot be modified. System Control Register 2 (SYSCR2) Bit 7 -- Initial value Read/Write 1 -- 6 -- 1 -- 5 -- 1 -- 4 NESEL 0 R/W 3 DTON 0 R/W 2 MSON 0 R/W 1 SA1 0 R/W 0 SA0 0 R/W SYSCR2 is an 8-bit read/write register for power-down mode control. Upon reset, SYSCR2 is initialized to H'E0. Bits 7 to 5--Reserved Bits: These bits are reserved; they are always read as 1, and cannot be modified. 89 Bit 4-- Noise Elimination Sampling Frequency Select (NESEL): This bit selects the frequency at which the watch clock signal (o W ) generated by the subclock pulse generator is sampled, in relation to the oscillator clock (oOSC) generated by the system clock pulse generator. When o OSC = 2 to 10 MHz, clear NESEL to 0. Bit 4: NESEL 0 1 Description Sampling rate is o OSC/16 Sampling rate is o OSC/4 (initial value) Bit 3--Direct Transfer on Flag (DTON): This bit designates whether or not to make direct transitions among active (high-speed), active (medium-speed) and subactive mode when a SLEEP instruction is executed. The mode to which the transition is made after the SLEEP instruction is executed depends on a combination of this and other control bits. Bit 3: DTON 0 Description * * 1 * When a SLEEP instruction is executed in active mode, a transition is made to standby mode, watch mode, or sleep mode. (initial value) When a SLEEP instruction is executed in subactive mode, a transition is made to watch mode or subsleep mode. When a SLEEP instruction is executed in active (high-speed) mode, a direct transition is made to active (medium-speed) mode if SSBY = 0, MSON = 1, and LSON = 0, or to subactive mode if SSBY = 1, TMA3 = 1, and LSON = 1. When a SLEEP instruction is executed in active (medium-speed) mode, a direct transition is made to active (high-speed) mode if SSBY = 0, MSON = 0, and LSON = 0, or to subactive mode if SSBY = 1, TMA3 = 1, and LSON = 1. When a SLEEP instruction is executed in subactive mode, a direct transition is made to active (high-speed) mode if SSBY = 1, TMA3 = 1, LSON = 0, and MSON = 0, or to active (medium-speed) mode if SSBY = 1, TMA3 = 1, LSON = 0, and MSON = 1. * * Bit 2--Medium Speed on Flag (MSON): After standby, watch, or sleep mode is cleared, this bit selects active (high-speed) or active (medium-speed) mode. Bit 2: MSON 0 1 Description Operation is in active (high-speed) mode Operation is in active (medium-speed) mode (initial value) 90 Bits 1 and 0--Subactive Mode Clock Select (SA1 and SA0): These bits select the CPU clock rate (oW /2, oW /4, or o W /8) in subactive mode. SA1 and SA0 cannot be modified in subactive mode. Bit 1: SA1 0 Bit 0: SA0 0 1 1 Note: * Don't care * Description oW/8 oW/4 oW/2 (initial value) 5.2 5.2.1 Sleep Mode Transition to Sleep Mode The system goes from active mode to sleep mode when a SLEEP instruction is executed while the SSBY and LSON bits in system control register 1 (SYSCR1) are cleared to 0. In sleep mode CPU operation is halted but the on-chip peripheral functions are operational. The CPU register contents are retained. 5.2.2 Clearing Sleep Mode Sleep mode is cleared by an interrupt (timer A, timer F, timer G, IRQ0 to IRQ4, WKP0 to WKP7, SCI1, SCI3, A/D converter) or by reset input. Clearing by Interrupt: When an interrupt is requested, sleep mode is cleared and interrupt exception handling starts. Operation resumes in active (high-speed) mode if MSON = 0 in SYSCR2, or active (medium-speed) mode if MSON = 1. Sleep mode is not cleared if the I bit of the condition code register (CCR) is set to 1 or the particular interrupt is disabled in the interrupt enable register. Clearing by Reset Input: When the RES pin goes low, the CPU goes into the reset state and sleep mode is cleared. 91 5.3 5.3.1 Standby Mode Transition to Standby Mode The system goes from active mode to standby mode when a SLEEP instruction is executed while the SSBY bit in SYSCR1 is set to 1, the LSON bit is cleared to 0, and bit TMA3 in timer mode register A (TMA) is cleared to 0. In standby mode the clock pulse generator stops, so the CPU and on-chip peripheral modules stop functioning. As long as a minimum required voltage is applied, the contents of the CPU registers and some on-chip peripheral function internal registers, and data in the on-chip RAM, will be retained. The I/O ports go to the high-impedance state. 5.3.2 Clearing Standby Mode Standby mode is cleared by an interrupt (IRQ0, IRQ1, WKP0 to WKP7) or by input at the RES pin. Clearing by Interrupt: When an interrupt is requested, the system clock pulse generator starts. After the time set in bits STS2 to STS0 in SYSCR1 has elapsed, a stable system clock signal is supplied to the entire chip, standby mode is cleared, and interrupt exception handling starts. Operation resumes in active (high-speed) mode if MSON = 0 in SYSCR2, or active (mediumspeed) mode if MSON = 1. Standby mode is not cleared if the I bit of CCR is set to 1 or the particular interrupt is disabled in the interrupt enable register. Clearing by RES Input: When the RES pin goes low, the system clock pulse generator starts. After the pulse generator output has stabilized, if the RES pin is driven high, the CPU starts reset exception handling. Since system clock signals are supplied to the entire chip as soon as the system clock pulse generator starts functioning, the RES pin should be kept at the low level until the pulse generator output stabilizes. 92 5.3.3 Oscillator Settling Time after Standby Mode is Cleared Bits STS2 to STS0 in SYSCR1 should be set as follows. When a Crystal Oscillator is Used: Table 5.4 gives settings for various operating frequencies. Set bits STS2 to STS0 for a waiting time of at least 10 ms. Table 5.4 STS2 0 0 0 0 1 Clock Frequency and Settling Time (times are in ms) STS1 0 0 1 1 * STS0 0 1 0 1 * Waiting Time 8,192 states 16,384 states 32,768 states 65,536 states 131,072 states 5 MHz 1.6 3.2 6.6 13.1 26.2 4 MHz 2.0 4.1 8.2 16.4 32.8 2 MHz 4.1 8.2 16.4 32.8 65.5 1 MHz 8.2 16.4 32.8 65.5 131.1 0.5 MHz 16.4 32.8 65.5 131.1 262.1 Note: * Don't care When an External Clock is Used: Any values may be set. Normally the minimum time (STS2 = STS1 = STS0 = 0) should be set. 93 5.3.4 Transition to Standby Mode and Pin States The system goes from active (high-speed) mode or active (medium-speed) mode to standby mode when a SLEEP instruction is executed while the SSBY bit in SYSCR1 is set to 1, the LSON bit in SYSCR1 is cleared to 0, and bit TMA3 in TMA is cleared to 0. At the same time, pins go to the high-impedance state (except pins with MOS pull-up turned on). The timing in this case is shown in figure 5.2. o Internal data bus SLEEP instruction fetch Next instruction fetch SLEEP instruction execution Internal processing High impedance Standby mode Pins Port output Active (high-speed) mode or active (medium-speed) mode Figure 5.2 Transition to Standby Mode and Pin States 94 5.4 5.4.1 Watch Mode Transition to Watch Mode The system goes from active or subactive mode to watch mode when a SLEEP instruction is executed while the SSBY bit in SYSCR1 is set to 1 and bit TMA3 in TMA is set to 1. In watch mode, operation of on-chip peripheral modules other than timer A is halted. As long as a minimum required voltage is applied, the contents of CPU registers and some registers of the onchip peripheral modules*, and the on-chip RAM contents, are retained. I/O ports keep the same states as before the transition. Note: * The contents of SCI3, DTMF generator registers are reset. 5.4.2 Clearing Watch Mode Watch mode is cleared by an interrupt (timer A, IRQ 0, WKP0 to WKP7) or by a low input at the RES pin. Clearing by Interrupt: When watch mode is cleared by a timer A, IRQ0, or WKP0 to WKP7 interrupt request, the mode to which a transition is made depends on the settings of LSON in SYSCR1 and MSON in SYSCR2. If both LSON and MSON are cleared to 0, transition is to active (high-speed) mode; if LSON = 0 and MSON = 1, transition is to active (medium-speed) mode; if LSON = 1, transition is to subactive mode. When the transition is to active mode, after the time set in SYSCR1 bits STS2 to STS0 has elapsed, a stable clock signal is supplied to the entire chip, watch mode is cleared, and interrupt exception handling starts. Watch mode is not cleared if the I bit of CCR is set to 1 or the particular interrupt is disabled in the interrupt enable register. Clearing by RES Input: Clearing by RES pin is the same as for standby mode; see 5.3.2, Clearing Standby Mode. 5.4.3 Oscillator Settling Time after Watch Mode is Cleared The waiting time is the same as for standby mode; see 5.3.3, Oscillator Settling Time after Standby Mode is Cleared. 95 5.5 5.5.1 Subsleep Mode Transition to Subsleep Mode The system goes from subactive mode to subsleep mode when a SLEEP instruction is executed while the SSBY bit in SYSCR1 is cleared to 0, LSON is set to 1, and bit TMA3 in TMA is set to 1. In subsleep mode, operation of on-chip peripheral modules other than timer A and timer G is halted. As long as a minimum required voltage is applied, the contents of CPU registers and some registers of the on-chip peripheral modules*, and the on-chip RAM contents, are retained. I/O ports keep the same states as before the transition. Note: * The contents of SCI3, DTMF generator registers are reset. 5.5.2 Clearing Subsleep Mode Subsleep mode is cleared by an interrupt (timer A, timer G, IRQ0 to IRQ4, WKP0 to WKP7) or by a low input at the RES pin. Clearing by Interrupt: When an interrupt is requested, subsleep mode is cleared and interrupt exception handling starts. Subsleep mode is not cleared if the I bit of CCR is set to 1 or the particular interrupt is disabled in the interrupt enable register. Clearing by RES Input: Clearing by RES input is the same as for standby mode; see 5.3.2, Clearing Standby Mode. 96 5.6 5.6.1 Subactive Mode Transition to Subactive Mode Subactive mode is entered from watch mode if a timer A, IRQ0, or WKP0 to WKP7 interrupt is requested while the LSON bit in SYSCR1 is set to 1. From subsleep mode, subactive mode is entered if a timer A, timer G, IRQ0 to IRQ4, or WKP0 to WKP7 interrupt is requested. A transition to subactive mode does not take place if the I bit of CCR is set to 1 or the particular interrupt is disabled in the interrupt enable register. The contents of SCI3, DTMF generator registers are reset. 5.6.2 Clearing Subactive Mode Subactive mode is cleared by a SLEEP instruction or by a low input at the RES pin. Clearing by SLEEP Instruction: If a SLEEP instruction is executed while the SSBY bit in SYSCR1 is set to 1 and bit TMA3 in TMA is set to 1, subactive mode is cleared and watch mode is entered. If a SLEEP instruction is executed while SSBY = 0 and LSON = 1 in SYSCR1 and TMA3 = 1 in TMA, subsleep mode is entered. Direct transfer to active mode is also possible; see 5.8, Direct Transfer, below. Clearing by RES Pin: Clearing by RES pin is the same as for standby mode; see 5.3.2, Clearing Standby Mode. 5.6.3 Operating Frequency in Subactive Mode The operating frequency in subactive mode is set in bits SA1 and SA0 in SYSCR2. The choices are oW /2, oW /4, and oW /8. 97 5.7 5.7.1 Active (medium-speed) Mode Transition to Active (medium-speed) Mode If the MSON bit in SYSCR2 is set to 1 while the LSON bit in SYSCR1 is cleared to 0, a transition to active (medium-speed) mode results from IRQ0, IRQ1, or WKP0 to WKP7 interrupts in standby mode, timer A, IRQ0, or WKP0 to WKP7 interrupts in watch mode, or any interrupt in sleep mode. A transition to active (medium-speed) mode does not take place if the I bit of CCR is set to 1 or the particular interrupt is disabled in the interrupt enable register. 5.7.2 Clearing Active (medium-speed) Mode Active (medium-speed) mode is cleared by a SLEEP instruction or by a low input at the reset. Clearing by SLEEP Instruction: A transition to standby mode takes place if a SLEEP instruction is executed while the SSBY bit in SYSCR1 is set to 1, the LSON bit in SYSCR1 is cleared to 0, and bit TMA3 in TMA is cleared to 0. The system goes to watch mode if the SSBY bit in SYSCR1 is set to 1 and bit TMA3 in TMA is set to 1 when a SLEEP instruction is executed. Sleep mode is entered if both SSBY and LSON are cleared to 0 when a SLEEP instruction is executed. Direct transfer to active (high-speed) mode or to subactive mode is also possible. See 5.8, Direct Transfer, below for details. Clearing by Reset: When the RES pin goes low, the CPU goes into the reset state and active (medium-speed) mode is cleared. 5.7.3 Operating Frequency in Active (medium-speed) Mode In active (medium-speed) mode, the CPU is clocked at 1/8 the frequency in active (high-speed) mode. The DTMF generator, however, continues to operate on the OSC clock (oOSC). 98 5.8 5.8.1 Direct Transfer Overview The CPU can execute programs in three modes: active (high-speed) mode, active (medium-speed) mode, and subactive mode. A direct transfer is a transition among these three modes without the stopping of program execution. A direct transfer can be made by executing a SLEEP instruction while the DTON bit in SYSCR2 is set to 1. After the mode transition, direct transfer interrupt exception handling starts. If the direct transfer interrupt is disabled in interrupt enable register 2 (IENR2), a transition is made instead to sleep mode or watch mode. Note that if a direct transition is attempted while the I bit in CCR is set to 1, sleep mode or watch mode will be entered, and it will be impossible to clear the resulting mode by means of an interrupt. Direct Transfer from Active (High-Speed) Mode to Active (Medium-Speed) Mode: When a SLEEP instruction is executed in active (high-speed) mode while the SSBY and LSON bits in SYSCR1 are cleared to 0, the MSON bit in SYSCR2 is set to 1, and the DTON bit in SYSCR2 is set to 1, a transition is made to active (medium-speed) mode via sleep mode. Direct Transfer from Active (High-Speed) Mode to Active (High-Speed) Mode: When a SLEEP instruction is executed in active (medium-speed) mode while the SSBY and LSON bits in SYSCR1 are cleared to 0, the MSON bit in SYSCR2 is cleared to 0, and the DTON bit in SYSCR2 is set to 1, a transition is made to active (high-speed) mode via sleep mode. Direct Transfer from Active (High-Speed) Mode to Subactive Mode: When a SLEEP instruction is executed in active (high-speed) mode while the SSBY and LSON bits in SYSCR1 are set to 1, the DTON bit in SYSCR2 is set to 1, and bit TMA3 in TMA is set to 1, a transition is made to subactive mode via watch mode. Direct Transfer from Subactive Mode to Active (High-Speed) Mode: When a SLEEP instruction is executed in subactive mode while the SSBY bit in SYSCR1 is set to 1, the LSON bit in SYSCR1 is cleared to 0, the MSON bit in SYSCR2 is cleared to 0, the DTON bit in SYSCR2 is set to 1, and bit TMA3 in TMA is set to 1, a transition is made directly to active (high-speed) mode via watch mode after the waiting time set in SYSCR1 bits STS2 to STS0 has elapsed. Direct Transfer from Active (Medium-Speed) Mode to Subactive Mode: When a SLEEP instruction is executed in active (medium-speed) mode while the SSBY and LSON bits in SYSCR1 are set to 1, the DTON bit in SYSCR2 is set to 1, and bit TMA3 in TMA is set to 1, a transition is made to subactive mode via watch mode. Direct Transfer from Subactive Mode to Active (Medium-Speed) Mode: When a SLEEP instruction is executed in subactive mode while the SSBY bit in SYSCR1 is set to 1, the LSON bit in SYSCR1 is cleared to 0, the MSON bit in SYSCR2 is set to 1, the DTON bit in SYSCR2 is set 99 to 1, and bit TMA3 in TMA is set to 1, a transition is made directly to active (medium-speed) mode via watch mode after the waiting time set in SYSCR1 bits STS2 to STS0 has elapsed. 5.8.2 Direct Transfer Time Time for Direct Transfer from Active (High-Speed) Mode to Active (Medium-Speed) Mode: When a SLEEP instruction is executed in active (high-speed) mode while the SSBY bit in SYSCR1 is cleared to 0, the LSON bit in SYSCR1 is cleared to 0, the MSON bit in SYSCR2 is set to 1, and the DTON bit in SYSCR2 is set to 1, a transition is made directly to active (medium-speed) mode. In this case, the time from execution of the SLEEP instruction to the end of interrupt exception handling (the direct transfer time) is given by equation (1) below: Direct transfer time ={ (Number of SLEEP instruction execution states) + (number of internal processing states) } x (tcyc before transition) + (number of interrupt exception handling execution states) x (tcyc after transition) ...................................................................... (1) Example: H8/3627 Series direct transfer time = (2 + 1) x 2tosc + 14 x 16tosc = 230tosc Legend: tosc: OSC clock cycle time tcyc: System clock (o) cycle time Time for Direct Transfer from Active (Medium-Speed) Mode to Active (High-Speed) Mode: When a SLEEP instruction is executed in active (medium-speed) mode while the SSBY bit in SYSCR1 is cleared to 0, the LSON bit in SYSCR1 is cleared to 0, the MSON bit in SYSCR2 is cleared to 0, and the DTON bit in SYSCR2 is set to 1, a transition is made directly to active (high-speed) mode. In this case, the time from execution of the SLEEP instruction to the end of interrupt exception handling (the direct transfer time) is given by equation (2) below: Direct transfer time ={ (Number of SLEEP instruction execution states) + (number of internal processing states) } x (tcyc before transition) + (number of interrupt exception handling execution states) x (tcyc after transition) ...................................................................... (2) Example: H8/3627 Series direct transfer time = (2 + 1) x 16tosc + 14 x 2tosc = 76tosc Legend: tosc: OSC clock cycle time tcyc: System clock (o) cycle time 100 Time for Direct Transfer from Subactive Mode to Active (High-Speed) Mode: When a SLEEP instruction is executed in subactive mode while the SSBY bit in SYSCR1 is set to 1, the LSON bit in SYSCR1 is cleared to 0, the MSON bit in SYSCR2 is cleared to 0, the DTON bit in SYSCR2 is set to 1, and bit TMA3 in TMA is set to 1, a transition is made directly to active (high-speed) mode. In this case, the time from execution of the SLEEP instruction to the end of interrupt exception handling (the direct transfer time) is given by equation (3) below: Direct transfer time ={ (Number of SLEEP instruction execution states) + (number of internal processing states) } x (tsubcyc before transition) + { (standby time set in STS2 to STS0) + (number of interrupt exception handling execution states) } x (tcyc after transition) ...................................................................... (3) Example: H8/3627 Series direct transfer time = (2 + 1) x 8tw + (8192 + 14) x 2tosc= 24tw + 16412tosc (When ow/8 CPU operating clock and 8192-state standby time are selected) Legend: tosc: OSC clock cycle time tw: Watch clock cycle time tcyc: System clock (o) cycle time tsubcyc : Subclock (oSUB) cycle time Time for Direct Transfer from Subactive Mode to Active (Medium-Speed) Mode: When a SLEEP instruction is executed in subactive mode while the SSBY bit in SYSCR1 is set to 1, the LSON bit in SYSCR1 is cleared to 0, the MSON bit in SYSCR2 is set to 1, the DTON bit in SYSCR2 is set to 1, and bit TMA3 in TMA is set to 1, a transition is made directly to active (medium-speed) mode. In this case, the time from execution of the SLEEP instruction to the end of interrupt exception handling (the direct transfer time) is given by equation (4) below: Direct transfer time ={ (Number of SLEEP instruction execution states) + (number of internal processing states) } x (tsubcyc before transition) + { (standby time set in STS2 to STS0) + (number of interrupt exception handling execution states) } x (tcyc after transition) ...................................................................... (4) Example: H8/3627 Series direct transfer time = (2 + 1) x 8tw + (8192 + 14) x 16tosc= 24tw + 13129tosc (When ow/8 CPU operating clock and 8192-state standby time are selected) Legend: tosc: OSC clock cycle time tw: Watch clock cycle time tcyc: System clock (o) cycle time tsubcyc : Subclock (oSUB) cycle time 101 102 Section 6 ROM 6.1 Overview The H8/3627 has 60 kbytes of on-chip mask ROM, while the H8/3626 has 48 kbytes the H8/3625 has 40 kbytes the H8/3624S has 32 kbytes the H8/3623S has 24 kbytes and the H8/3622S has 16 kbytes. The H8/3627 also has 60 kbytes of on-chip PROM. The ROM is connected to the CPU by a 16-bit data bus, allowing high-speed 2-state access for both byte data and word data. 6.1.1 Block Diagram Figure 6.1 shows a block diagram of the on-chip ROM. Internal data bus (upper 8 bits) Internal data bus (lower 8 bits) H'0000 H'0002 H'0000 H'0002 H'0001 H'0003 On-chip ROM H'EDFE H'EDFE Even-numbered address H'EDFF Odd-numbered address Figure 6.1 ROM Block Diagram (H8/3627) 103 6.2 6.2.1 PROM Mode Selection of PROM Mode If the on-chip ROM is PROM, setting the chip to PROM mode stops operation as a microcomputer and allows the on-chip PROM to be programmed in the same way as the HN27C101, except that page programming is not supported. Table 6.1 shows how to set PROM mode. Table 6.1 Pin Name TEST PB7/AN7 PB6/AN6 Setting PROM Mode Setting High level Low level 6.2.2 Socket Adapter Pin Arrangement and Memory Map A standard PROM programmer can be used to program the PROM. A socket adapter is required for conversion to 32 pins. Figure 6.2 shows the pin-to-pin wiring of the socket adapter. Figure 6.3 shows a memory map. 104 H8/3627 FP-64A Pin FP-64E 8 RES P60 36 P61 37 P62 38 P63 39 P64 40 P65 41 P66 42 P67 43 P87 59 P86 58 P85 57 P84 56 P83 55 P82 54 P81 53 P80 52 P70 44 P27 16 P72 46 P73 47 P74 48 P75 49 P76 50 P14 20 P15 19 51 P77 P71 45 P13 21 VCC 7 CVCC 64 TEST 6 X1 1 P11 23 P12 22 P16 18 VSS 3 62 PB7 63 PB6 Note: Pins not indicated in the figure should be left open. Pin VPP EO0 EO1 EO2 EO3 EO4 EO5 EO6 EO7 EA0 EA1 EA2 EA3 EA4 EA5 EA6 EA7 EA8 EA9 EA10 EA11 EA12 EA13 EA14 EA15 EA16 CE OE PGM VCC EPROM socket HN27C101 (32 pins) 1 13 14 15 17 18 19 20 21 12 11 10 9 8 7 6 5 27 26 23 25 4 28 29 3 2 22 24 31 32 VSS 16 Figure 6.2 Socket Adapter Pin Correspondence 105 Address in MCU mode H'0000 Address in PROM mode H'0000 On-chip PROM H'EDFF H'EDFF Unused area* H'1FFFF Note: * Unpredictable data may be output if this area is read in PROM mode. When programming with a PROM programmer, be sure to specify addresses from H'0000 to H'EDFF. If H'EE00 and higher addresses are programmed by mistake, it may become impossible to program or verify the PROM. When programming, specify H'FF for this address area (H'EE00 to H'1FFFF). Figure 6.3 Memory Map in PROM Mode 106 6.3 Programming The program, verify, and other modes are selected as shown in table 6.2 in PROM mode. Table 6.2 Mode Selection in PROM Mode Pin Mode Write Verify Programming disabled CE L L L L H H Legend: L: Low level H: High level VPP : VPP level VCC: VCC level OE H L L H L H PGM L H L H L H VPP VPP VPP VPP VCC VCC VCC VCC EO7 to EO0 Data input Data output EA 16 to EA0 Address input Address input High impedance Address input The programming and verifying specifications in PROM mode are the same as the specifications of the standard HN27C101 EPROM. Page programming is not supported, however. The PROM programmer must not be set to page mode. PROM programmers that support only page programming cannot be used. When selecting a PROM programmer, make sure that it supports a byte-by-byte high-speed, high-reliability programming method. Be sure to set the address range to H'0000 to H'EDFF. 107 6.3.1 Programming and Verification An efficient, high-speed, high-reliability programming procedure can be used to program and verify data. This procedure programs the chip quickly without subjecting it to voltage stress and without sacrificing data reliability. Data in unused address areas is H'FF. Figure 6.4 shows the basic high-speed, high-reliability programming flow chart. Start Set program/verify mode VCC = 6.0 V 0.25 V, VPP = 12.5 V 0.3 V Address = 0 n=0 n+1 n No Yes n < 25 No Verification OK? Yes Overprogram with t OPW = 0.2n ms No Program with t PW = 0.2 ms 5% Address + 1 address Last address? Yes Set read mode VCC = 5.0 V 0.25 V, VPP = VCC No Fail All addresses read? Yes End Figure 6.4 High-Speed, High-Reliability Programming Flow Chart 108 Table 6.3 and table 6.4 give the electrical characteristics in programming mode. Table 6.3 DC Characteristics (Conditions: VCC = 6.0 V 0.25 V, VPP = 12.5 V 0.3 V, VSS = 0 V, Ta = 25C 5C) Item Input highlevel voltage Input lowlevel voltage Output highlevel voltage Output lowlevel voltage EO7 to EO 0, EA16 to EA 0 OE, CE, PGM EO7 to EO 0, EA16 to EA 0 OE, CE, PGM EO7 to EO 0 EO7 to EO 0 Symbol VIH VIL VOH VOL |ILI| I CC I PP Min 2.4 -0.3 2.4 -- -- -- -- Typ -- -- -- -- -- -- -- Max VCC + 0.3 0.8 -- 0.45 2 40 40 Unit V V V V A mA mA I OH = -200 A I OL = 0.8 mA Vin = 5.25 V/ 0.5 V Test Condition Input leakage EO7 to EO 0, EA16 to EA 0 current OE, CE, PGM VCC current VPP current 109 Table 6.4 AC Characteristics (Conditions: VCC = 6.0 V 0.25 V, VPP = 12.5 V 0.3 V, Ta = 25C 5C) Item Address setup time OE setup time Data setup time Address hold time Data hold time Data output disable time VPP setup time Programming pulse width PGM pulse width for overprogramming VCC setup time CE setup time Data output delay time Symbol t AS t OES t DS t AH t DH t DF * t VPS t PW t OPW* t VCS t CES t OE 3 2 Min 2 2 2 0 2 -- 2 0.19 0.19 2 2 0 Typ -- -- -- -- -- -- -- 0.20 -- -- -- -- Max -- -- -- -- -- 130 -- 0.21 5.25 -- -- 200 Unit s s s s s ns s ms ms s s ns Test Conditions Figure 6.5* 1 Notes: 1. Input pulse level: 0.45 V to 2.4 V Input rise time/fall time 20 ns Timing reference levels: Input: 0.8 V, 2.0 V Output: 0.8 V, 2.0 V 2. t DF is defined at the point at which the output is floating and the output level cannot be read. 3. t OPW is defined by the value given in the hi-speed, hi-reliability programming flow chart in figure 6.4. 110 Figure 6.5 shows a program/verify timing diagram. Program Address tAS Data tDS VPP VPP VCC VCC+1 VCC tVCS tVPS Input data tDH tAH Output data tDF Verify VCC CE tCES PGM tPW OE tOPW* tOES tOE Note: * tOPW is defined by the value given in the high-speed, high-reliability programming flow chart in figure 6.4. Figure 6.5 PROM Program/Verify Timing 111 6.3.2 Programming Precautions * Use the specified programming voltage and timing. The programming voltage in PROM mode (VPP) is 12.5 V. Use of a higher voltage can permanently damage the chip. Be especially careful with respect to PROM programmer overshoot. Setting the PROM programmer to Hitachi specifications for the HN27C101 will result in correct VPP of 12.5 V. * Make sure the index marks on the PROM programmer socket, socket adapter, and chip are properly aligned. If they are not, the chip may be destroyed by excessive current flow. Before programming, be sure that the chip is properly mounted in the PROM programmer. * Avoid touching the socket adapter or chip while programming, since this may cause contact faults and write errors. * Select the programming mode carefully. The chip cannot be programmed in page programming mode. * When programming with a PROM programmer, be sure to specify addresses from H'0000 to H'EDFF. If address H'EE00 and higher addresses are programmed by mistake, it may become impossible to program the PROM or verify the programmed data. When programming, assign H'FF data to the address area from H'EE00 to H'1FFFF. 112 6.4 Reliability of Programmed Data A highly effective way of assuring data retention characteristics after programming is to screen the chips by baking them at a temperature of 150C. This quickly eliminates PROM memory cells causing initial data retention failure. Figure 6.6 shows a flowchart of this screening procedure. Write program and verify contents Bake at high temperature with power off 125C to 150C, 24 hrs to 48 hrs Read and check program Install Figure 6.6 Recommended Screening Procedure If write errors occur repeatedly while the same PROM programmer is being used, stop programming and check for problems in the PROM programmer and socket adapter, etc. Please notify your Hitachi representative of any problems occurring during programming or in screening after high-temperature baking. 113 114 Section 7 RAM 7.1 Overview The H8/3627 Series has 1 kbyte or 2 kbytes of high-speed static RAM on-chip. The RAM is connected to the CPU by a 16-bit data bus, allowing high-speed 2-state access for both byte data and word data. 7.1.1 Block Diagram Figure 7.1 shows a block diagram of the on-chip RAM. Internal data bus (upper 8 bits) Internal data bus (lower 8 bits) H'F780 H'F782 H'F780 H'F782 H'F781 H'F783 On-chip RAM H'FF7E H'FF7E Even-numbered address H'FF7F Odd-numbered address Figure 7.1 RAM Block Diagram (Example of 2 kbytes RAM) 115 116 Section 8 I/O Ports 8.1 Overview The H8/3627 Series is provided with five 8-bit I/O ports, one 7-bit I/O port, one 3-bit I/O port, one 2-bit input-only port, and one 1-bit input-only port. Table 8.1 indicates the functions of each port. Each port has of a port control register (PCR) that controls input and output, and a port data register (PDR) for storing output data. Input or output can be controlled by individual bits. See 2.9.2, Notes on Bit Manipulation, for information on executing bit-manipulation instructions to write data in PCR or PDR. Block diagrams of each port are given in Appendix C, I/O Port Block Diagrams. 117 Table 8.1 Port Functions Function Switching Register PMR1 TCRF Port Port 1 Description * 8-bit I/O port * Input pull-up MOS option Pins P17 to P1 5/ IRQ3 to IRQ1/ TMIF P14 P13/TMIG Other Functions External interrupts 3 to 1 Timer event input TMIF None Timer G input capture PMR1 PMR1 PMR1 PMR2 SCR3 SMR3 PMR6 P12, P11/TMOFH, Timer F output compare TMOFL P10/TMOW Port 2 * 1-bit input-only port P27 * 7-bit I/O port * Input pull-up MOS option P26/TXD P25/RXD P24/SCK3 P23/SO 1 P22/SI1 P21/SCK1 P20/IRQ4/ ADTRG Port 5 * 8-bit I/O port * Input pull-up MOS option Port 6 * 8-bit I/O port * Input pull-up MOS option Port 7 Port 8 Port A Port B * 8-bit I/O port * 8-bit I/O port * 3-bit I/O port * 2-bit input port P77 to P7 0 P87 to P8 0 PA3 to PA 1 None None None P57 to P5 0/ WKP 7 to WKP 0 External interrupt 4 and A/D converter external trigger Wakeup input (WKP 7 to WKP 0) SCI1 data output (SO1), data input (SI1), clock input/output (SCK1) Timer A clock output External interrupt 0 SCI3 data output (TXD), data input (RXD), clock input/output (SCK3) PMR2 PMR2 PMR5 P67 to P6 0 None PB7, PB6/AN7, AN 6 A/D converter analog input AMR 118 8.2 8.2.1 Port 1 Overview Port 1 is an 8-bit I/O port. Figure 8.1 shows its pin configuration. P17/IRQ3/TMIF P16/IRQ2 P15/IRQ1 Port 1 P14 P13/TMIG P12/TMOFH P11/TMOFL P10/TMOW Figure 8.1 Port 1 Pin Configuration 8.2.2 Register Configuration and Description Table 8.2 shows the port 1 register configuration. Table 8.2 Name Port data register 1 Port control register 1 Port pull-up control register 1 Port mode register 1 Port 1 Registers Abbrev. PDR1 PCR1 PUCR1 PMR1 R/W R/W W R/W R/W Initial Value H'00 H'00 H'00 H'00 Address H'FFD4 H'FFE4 H'FF9C H'FF98 119 Port Data Register 1 (PDR1) Bit 7 P17 Initial value Read/Write 0 R/W 6 P16 0 R/W 5 P15 0 R/W 4 P14 0 R/W 3 P13 0 R/W 2 P12 0 R/W 1 P11 0 R/W 0 P10 0 R/W PDR1 is an 8-bit register that stores data for pins P17 to P10 of port 1. If port 1 is read while PCR1 bits are set to 1, the values stored in PDR1 are directly read, regardless of the actual pin states. If port 1 is read while PCR1 bits are cleared to 0, the pin states are read. Upon reset, PDR1 is initialized to H'00. Port Control Register 1 (PCR1) Bit 7 PCR17 Initial value Read/Write 0 W 6 PCR16 0 W 5 PCR15 0 W 4 PCR14 0 W 3 PCR13 0 W 2 PCR12 0 W 1 PCR11 0 W 0 PCR10 0 W PCR1 is an 8-bit register for controlling whether each of the port 1 pins P17 to P10 functions as an input pin or output pin. Setting a PCR1 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. The settings in PCR1 and in PDR1 are valid only when the corresponding pin is designated in PMR1 as a general I/O pin. Upon reset, PCR1 is initialized to H'00. PCR1 is a write-only register. All bits are read as 1. Port Pull-Up Control Register 1 (PUCR1) Bit 7 6 5 4 3 2 1 0 PUCR17 PUCR16 PUCR15 PUCR14 PUCR13 PUCR12 PUCR11 PUCR10 Initial value Read/Write 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W PUCR1 controls whether the MOS pull-up of each port 1 pins P17 to P10 is on or off. When a PCR1 bit is cleared to 0, setting the corresponding PUCR1 bit to 1 turns on the MOS pull-up for the corresponding pin, while clearing the bit to 0 turns off the MOS pull-up. Upon reset, PUCR1 is initialized to H'00. 120 Port Mode Register 1 (PMR1) Bit 7 IRQ3 Initial value Read/Write 0 R/W 6 IRQ2 0 R/W 5 IRQ1 0 R/W 4 -- 0 -- 3 TMIG 0 R/W 2 TMOFH 0 R/W 1 TMOFL 0 R/W 0 TMOW 0 R/W PMR1 is an 8-bit read/write register, controlling the selection of pin functions for port 1 pins. Upon reset, PMR1 is initialized to H'00. Bit 7--P17/IRQ3/TMIF Pin Function Switch (IRQ3): This bit selects whether pin P1 7/IRQ3/TMIF is used as P17 or as IRQ3/TMIF. Bit 7: IRQ3 0 1 Description Functions as P1 7 I/O pin Functions as IRQ3/TMIF input pin (initial value) Note: Rising or falling edge sensing can be designated for IRQ3/TMIF. For information about TMIF pin settings, see 9.3.2 (3), Timer Control Register F (TCRF). Bit 6--P16/IRQ2 Pin Function Switch (IRQ2): This bit selects whether pin P16/IRQ2 is used as P1 6 or as IRQ2. Bit 6: IRQ2 0 1 Description Functions as P1 6 I/O pin Functions as IRQ2 input pin (initial value) Note: Rising or falling edge sensing can be designated for IRQ2. Bit 5--P15/IRQ1 Pin Function Switch (IRQ1): This bit selects whether pin P15/IRQ1 is used as P1 5 or as IRQ1. Bit 5: IRQ1 0 1 Description Functions as P1 5 I/O pin Functions as IRQ1 input pin (initial value) Note: Rising or falling edge sensing can be designated for IRQ1. Bit 4--Reserved Bit: Bit 4 is reserved: it is a always read as 0, and should be used cleared to 0. 121 Bit 3--P13/TMIG Pin Function Switch (TMIG): This bit selects whether pin P13/TMIG is used as P13 or as TMIG. Bit 3: TMIG 0 1 Description Functions as P1 3 I/O pin Functions as TMIG input pin (initial value) Bit 2--P12/TMOFH Pin Function Switch (TMOFH): This bit selects whether pin P12/TMOFH is used as P12 or as TMOFH. Bit 2: TMOFH 0 1 Description Functions as P1 2 I/O pin Functions as TMOFH output pin (initial value) Bit 1--P11/TMOFL Pin Function Switch (TMOFL): This bit selects whether pin P11/TMOFL is used as P11 or as TMOFL. Bit 1: TMOFL 0 1 Description Functions as P1 1 I/O pin Functions as TMOFL output pin (initial value) Bit 0--P10/TMOW Pin Function Switch (TMOW): This bit selects whether pin P10/TMOW is used as P10 or as TMOW. Bit 0: TMOW 0 1 Description Functions as P1 0 I/O pin Functions as TMOW output pin (initial value) 122 8.2.3 Pin Functions Table 8.3 shows the port 1 pin functions. Table 8.3 Pin P17/IRQ3/TMIF Port 1 Pin Functions Pin Functions and Selection Method The pin function depends on bit IRQ3 in PMR1, bits CKSL2 to CKSL0 in TCRF, and bit PCR1 7 in PCR1. IRQ3 PCR17 CKSL2 to CKSL0 Pin function P17 input pin 0 * 0 1 Not 0** P17 output pin IRQ3 input pin 1 * 0** IRQ3/TMIF input pin Note: When using this pin for TMIF input, clear bit IEN3 to 0 in IENR1 to disable IRQ3 interrupts. P16/IRQ2 The pin function depends on bit IRQ2 in PMR1, bit PCR16 in PCR1. IRQ2 PCR16 Pin function P15/IRQ1 0 P16 input pin 0 1 P16 output pin 1 * IRQ2 input pin The pin function depends on bit IRQ1 in PMR1 and bit PCR15 in PCR1. IRQ1 PCR15 Pin function 0 P15 input pin 0 1 P15 output pin 1 * IRQ1 input pin P14 The pin function depends on bit PCR14 in PCR1. PCR14 Pin function 0 P14 input pin 1 P14 output pin P13/TMIG The pin function depends on bit TMIG in PMR1 and bit PCR1 3 in PCR1. TMIG PCR13 Pin function 0 P13 input pin 0 1 P13 output pin 1 * TMIG input pin 123 Table 8.3 Pin P12/TMOFH Port 1 Pin Functions (cont) Pin Functions and Selection Method The pin function depends on bit TMOFH in PMR1 and bit PCR12 in PCR1. TMOFH PCR12 Pin function 0 P12 input pin 0 1 P12 output pin 1 * TMOFH output pin P11/TMOFL The pin function depends on bit TMOFL in PMR1 and bit PCR1 1 in PCR1. TMOFL PCR11 Pin function 0 P11 input pin 0 1 P11 output pin 1 * TMOFL output pin P10/TMOW The pin function depends on bit TMOW in PMR1 and bit PCR1 0 in PCR1. TMOW PCR10 Pin function 0 P10 input pin 0 1 P10 output pin 1 * TMOW output pin Note: * Don't care 8.2.4 Pin States Table 8.4 shows the port 1 pin states in each operating mode. Table 8.4 Pins P17/IRQ3/TMIF P16/IRQ2 P15/IRQ1 P14 P13/TMIG P12/TMOFH P11/TMOFL P10/TMOW Note: * A high-level signal is output when the MOS pull-up is in the on state. Port 1 Pin States Reset Sleep Subsleep Standby Watch Subactive Active HighRetains Retains impedance previous previous state state HighRetains Functional Functional impedance* previous state 124 8.2.5 MOS Input Pull-Up Port 1 has a built-in MOS input pull-up function that can be controlled by software. When a PCR1 bit is cleared to 0, setting the corresponding PUCR1 bit to 1 turns on the MOS pull-up for that pin. The MOS input pull-up function is in the off state after a reset. PCR1n PUCR1n MOS input pull-up Note: * Don't care (n = 7 to 0) 0 Off 0 1 On 1 * Off 125 8.3 8.3.1 Port 2 Overview Port 2 is an 7-bit I/O port and 1-bit input port. Figure 8.2 shows its pin configuration. P27/IRQ0 P26/TXD P25/RXD Port 2 P24/SCK3 P23/SO1 P22/SI1 P21/SCK1 P20/IRQ4/ADTRG Figure 8.2 Port 2 Pin Configuration 8.3.2 Register Configuration and Description Table 8.5 shows the port 2 register configuration. Table 8.5 Name Port data register 2 Port control register 2 Port mode register 2 Port mode register 6 Port pull-up control register 2 Port 2 Registers Abbrev. PDR2 PCR2 PMR2 PMR6 PUCR2 R/W R/W W R/W R/W R/W Initial Value H'00 H'00 H'40 H'F8 H'00 Address H'FFD5 H'FFE5 H'FF99 H'FF9A H'FF9D 126 Port Data Register 2 (PDR2) Bit 7 P27 Initial value Read/Write 0 R/W 6 P26 0 R/W 5 P25 0 R/W 4 P24 0 R/W 3 P23 0 R/W 2 P22 0 R/W 1 P21 0 R/W 0 P20 0 R/W PDR2 is an 8-bit register that stores data for pins P27 to P20 of port 2. If port 2 is read while PCR2 bits are set to 1, the values stored in PDR2 are directly read, regardless of the actual pin states. If port 2 is read while PCR2 bits are cleared to 0, the pin states are read. Upon reset, PDR2 is initialized to H'00. Port Control Register 2 (PCR2) Bit 7 PCR27 Initial value Read/Write 0 W 6 PCR26 0 W 5 PCR25 0 W 4 PCR24 0 W 3 PCR23 0 W 2 PCR22 0 W 1 PCR21 0 W 0 PCR20 0 W PCR2 is an 8-bit register for controlling whether each of the port 2 pins P27 to P20 functions as an input pin or output pin. Setting a PCR2 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. The settings in PCR2 and in PDR2 are valid only when the corresponding pin is designated in PMR2 as a general I/O pin. Upon reset, PCR2 is initialized to H'00. PCR2 is a write-only register, which always reads all 1s. Note: As P27 is an input-only pin, it becomes a high-impedance output when PCR27 is set to 1. 127 Port Mode Register 2 (PMR2) Bit 7 IRQ0 Initial value Read/Write 0 R/W 6 -- 1 -- 5 POF1 0 R/W 4 NCS 0 R/W 3 SO1 0 R/W 2 SI1 0 R/W 1 SCK1 0 R/W 0 IRQ4 0 R/W PMR2 is an 8-bit read/write register for controlling the selection of pin functions for pins P2 0 to P2 3 and P27, controlling the PMOS on/off option for pin P23/SO 1, and controlling the TMIG input noise canceller. Upon reset, PMR2 is initialized to H'40. Bits 7--P27/IRQ0 Pin Function Switch (IRQ0): This bit selects whether pin P27/IRQ0 is used as P2 7 or as IRQ0. Bit 7: IRQ0 0 1 Description Functions as P2 7 input pin Functions as IRQ0 input pin (initial value) Bit 6--Reserved Bit: Bit 6 is reserved: it is always read as 1, and cannot be modified. Bit 5--P23/SO1 pin PMOS control (POF1): This bit turns on and off the PMOS transistor in the P2 3/SO 1 pin output buffer. Bit 5: POF1 0 1 Description CMOS output NMOS open-drain output (initial value) Bit 4--TMIG noise canceller select (NCS): This bit controls the noise canceller circuit for input capture at pin TMIG. Bit 4: NCS 0 1 Description Noise canceller function not selected Noise canceller function selected (initial value) 128 Bit 3--P23/SO1 Pin Function Switch (SO1): This bit selects whether pin P23/SO1 is used as P23 or as SO1. Bit 3: SO1 0 1 Description Functions as P2 3 I/O pin Functions as SO 1 output pin (initial value) Bit 2--P22/SI1 Pin Function Switch (SI1): This bit selects whether pin P22/SI1 is used as P22 or as SI1. Bit 2: SI1 0 1 Description Functions as P2 2 I/O pin Functions as SI1 input pin (initial value) Bit 1--P21/SCK1 Pin Function Switch (SCK1): This bit selects whether pin P21/SCK1 is used as P2 1 or as SCK 1. Bit 1: SCK1 0 1 Description Functions as P2 1 I/O pin Functions as SCK1 I/O pin (initial value) Bit 0--P20/IRQ4/ADTRG Pin Function Switch (IRQ4): This bit selects whether pin P2 0/IRQ4/ADTRG is used as P20 or as IRQ4/ADTRG. Bit 0: IRQ4 0 1 Description Functions as P2 0 I/O pin Functions as IRQ4/ADTRG input pin (initial value) Note: For information about ADTRG pin settings, see 12.3.2, Start of A/D Conversion by External Trigger Input. 129 Port Mode Register 6 (PMR6) Bit 7 -- Initial value Read/Write 1 -- 6 -- 1 -- 5 -- 1 R/W 4 -- 1 R/W 3 -- 1 -- 2 TXD 0 R/W 1 -- 0 R/W 0 -- 0 R/W Bits 7, 6, and 3: Reserved Bits: Bits 7, 6, and 3 are reserved bits. They are always read as 1 and cannot be modified. Bit 5, 4--Reserved Bit: Bit 5, 4 is reserved: it should be used set to 1. Bit 2--P26/TXD Pin Function Switch (TXD): This bits selects whether the P26/TXD pin is used as P26 or as TXD. Bit 2: TXD 0 1 Description Functions as P2 6 I/O pin Functions as TXD output pin (initial value) Bits 1 and 0--Reserved Bits: Bits 1 and 0 are reserved: they should be used cleared to 0. Port Pull-Up Control Register 2 (PUCR2) Bit 7 6 5 4 3 2 1 0 PUCR27 PUCR26 PUCR25 PUCR24 PUCR23 PUCR22 PUCR21 PUCR20 Initial value Read/Write 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W PUCR2 controls whether the MOS pull-up of each port 2 pin is on or off. When a PCR2 bit is cleared to 0, setting the corresponding PUCR2 bit to 1 turns on the MOS pull-up for the corresponding pin, while clearing the bit to 0 turns off the MOS pull-up. Upon reset, PUCR2 is initialized to H'00. Note: As P27 is an input-only pin, the MOS pull-up is turned off regardless of whether PUCR27 is set to 1 or cleared to 0. 130 8.3.3 Pin Functions Table 8.6 shows the port 2 pin functions. Table 8.6 Pin P27/IRQ0 Port 2 Pin Functions Pin Functions and Selection Method The pin function depends on bit IRQ0 in PMR2 and bit PCR27 in PCR2. IRQ0 PCR27 Pin function 0 P27 input pin 0 1 Highimpedance 1 * IRQ0 input pin P26/TXD The pin function depends on bit TXD in PMR6 and bit PCR26 in PCR2. TXD PCR26 Pin function 0 P26 input pin 0 1 P26 output pin 1 * TXD output pin P25/RXD The pin function depends on bit RE in SCR of SCI3 and bit PCR25 in PCR2. RE PCR25 Pin function 0 P25 input pin 0 1 P25 output pin 1 * RXD input pin P24/SCK3 The pin function depends on bits CKE1 and CKE0 in SCR of SCI3, bit COM in SMR of SCI3, and bit PCR24 in PCR2. CKE1 CKE0 COM PCR24 Pin function 0 P24 input pin 0 0 1 P24 output pin 0 0 1 * SCK 3 output pin 1 * 1 * * * SCK 3 input pin P23/SO 1 The pin function depends on bit SO1 in PMR2 and bit PCR23 in PCR2. SO1 PCR23 Pin function 0 P23 input pin 0 1 P23 output pin 1 * SO1 output pin 131 Table 8.6 Pin P22/SI1 Port 2 Pin Functions (cont) Pin Functions and Selection Method The pin function depends on bit SI1 in PMR2 and bit PCR2 2 in PCR2. SI1 PCR22 Pin function 0 P22 input pin 0 1 P22 output pin 1 * SI 1 input pin P21/SCK1 The pin function depends on bit SCK1 in PMR2, bit CKS3 in SCR1, and bit PCR21 in PCR2. SCK1 CKS 3 PCR21 Pin function 0 P21 input pin 0 * 1 P21 output pin 0 * SCK 1 output pin 1 1 * SCK 1 input pin P20/IRQ4/ ADTRG The pin function depends on bit IRQ4 in PMR2, bit TRGE in AMR, and bit PCR20 in PCR2. IRQ4 PCR20 TRGE Pin function P20 input pin 0 * P20 output pin 0 1 0 IRQ4 input pin 1 * 1 IRQ4/ADTRG input pin Note: When using this pin for ADTRG input, clear bit IEN4 to 0 in IENR1 to disable IRQ4 interrupts. Note: * Don't care 132 8.3.4 Pin States Table 8.7 shows the port 2 pin states in each operating mode. Table 8.7 Pins P27/IRQ0 P26/TXD P25/RXD P24/SCK3 P23/SO 1 P22/SI1 P21/SCK1 P20/IRQ4/ ADTRG Note: * High level output if the MOS pull-up is on. Port 2 Pin States Reset Sleep Subsleep Standby Watch Subactive Active HighHighHighHighHighHighHighimpedance impedance impedance impedance impedance impedance impedance HighRetains impedance previous state Retains previous state HighRetains impedance* previous state Functional Functional 8.3.5 MOS Input Pull-Up Port 2 has a built-in MOS input pull-up function that can be controlled by software. When a PCR2 bit is cleared to 0, setting the corresponding PUCR2 bit to 1 turns on the MOS pull-up for that pin. The MOS input pull-up function is in the off state after a reset. PCR2n PUCR2n MOS input pull-up Note: * Don't care (n = 6 to 0) 0 Off 0 1 On 1 * Off Note: As P27 is an input-only pin, the MOS pull-up is turned off regardless of whether PUCR27 is set to 1 or cleared to 0. 133 8.4 8.4.1 Port 5 Overview Port 5 is an 8-bit I/O port, configured as shown in figure 8.3. P5 7 /WKP7 P5 6 /WKP6 P5 5 /WKP5 Port 5 P5 4 /WKP4 P5 3 /WKP3 P5 2 /WKP2 P5 1 /WKP1 P5 0 /WKP0 Figure 8.3 Port 5 Pin Configuration 8.4.2 Register Configuration and Description Table 8.8 shows the port 5 register configuration. Table 8.8 Name Port data register 5 Port control register 5 Port pull-up control register 5 Port mode register 5 Port 5 Registers Abbrev. PDR5 PCR5 PUCR5 PMR5 R/W R/W W R/W R/W Initial Value H'00 H'00 H'00 H'00 Address H'FFD8 H'FFE8 H'FF9E H'FF9B 134 Port Data Register 5 (PDR5) Bit 7 P57 Initial value Read/Write 0 R/W 6 P56 0 R/W 5 P55 0 R/W 4 P54 0 R/W 3 P53 0 R/W 2 P52 0 R/W 1 P51 0 R/W 0 P50 0 R/W PDR5 is an 8-bit register that stores data for port 5 pins P57 to P50. If port 5 is read while PCR5 bits are set to 1, the values stored in PDR5 are directly read, regardless of the actual pin states. If port 5 is read while PCR5 bits are cleared to 0, the pin states are read. Upon reset, PDR5 is initialized to H'00. Port Control Register 5 (PCR5) Bit 7 PCR57 Initial value Read/Write 0 W 6 PCR56 0 W 5 PCR55 0 W 4 PCR54 0 W 3 PCR53 0 W 2 PCR52 0 W 1 PCR51 0 W 0 PCR50 0 W PCR5 is an 8-bit register for controlling whether each of the port 5 pins P57 to P50 functions as an input pin or output pin. Setting a PCR5 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. The settings in PCR5 and in PDR5 are valid only when the corresponding pin is designated as a general I/O pin in PMR5. Upon reset, PCR5 is initialized to H'00. PCR5 is a write-only register. All bits are read as 1. Port Pull-Up Control Register 5 (PUCR5) Bit 7 6 5 4 3 2 1 0 PUCR57 PUCR56 PUCR55 PUCR54 PUCR53 PUCR52 PUCR51 PUCR50 Initial value Read/Write 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W PUCR5 controls whether the MOS pull-up of each port 5 pin is on or off. When a PCR5 bit is cleared to 0, setting the corresponding PUCR5 bit to 1 turns on the MOS pull-up for the corresponding pin, while clearing the bit to 0 turns off the MOS pull-up. Upon reset, PUCR5 is initialized to H'00. 135 Port Mode Register 5 (PMR5) Bit 7 WKP 7 Initial value Read/Write 0 R/W 6 WKP 6 0 R/W 5 WKP 5 0 R/W 4 WKP 4 0 R/W 3 WKP 3 0 R/W 2 WKP 2 0 R/W 1 WKP 1 0 R/W 0 WKP 0 0 R/W PMR5 is an 8-bit read/write register, controlling the selection of pin functions for port 5 pins. Upon reset, PMR5 is initialized to H'00. Bit n: P5n/WKPn Pin Function Switch (WKPn): This bit selects whether it is used as P5 n or as WKPn. Bit n: WKPn 0 1 Description Functions as P5 n I/O pin Functions as WKP n input pin (n = 7 to 0) (initial value) 8.4.3 Pin Functions Table 8.9 shows the port 5 pin functions. Table 8.9 Pin P57/WKP 7 to P50/WKP 0 Port 5 Pin Functions Pin Functions and Selection Method The pin function depends on bit WKP n in PMR5 and bit PCR5n in PCR5. (n = 7 to 0) WKP n PCR5n Pin function 0 P5n input pin 0 1 P5n output pin 1 * WKP n input pin Note: * Don't care 136 8.4.4 Pin States Table 8.10 shows the port 5 pin states in each operating mode. Table 8.10 Port 5 Pin States Pins P57/WKP 7 to P50/WKP 0 Reset Sleep Subsleep Standby Watch Subactive Active HighRetains Retains impedance previous previous state state HighRetains Functional Functional impedance* previous state Note: * A high-level signal is output when the MOS pull-up is in the on state. 8.4.5 MOS Input Pull-Up Port 5 has a built-in MOS input pull-up function that can be controlled by software. When a PCR5 bit is cleared to 0, setting the corresponding PUCR5 bit to 1 turns on the MOS pull-up for that pin. The MOS pull-up function is in the off state after a reset. PCR5n PUCR5n MOS input pull-up Note: * Don't care (n = 7 to 0) 0 Off 0 1 On 1 * Off 137 8.5 8.5.1 Port 6 Overview Port 6 is an 8-bit I/O port, configured as shown in figure 8.4. P6 7 P6 6 P6 5 Port 6 P6 4 P6 3 P6 2 P6 1 P6 0 Figure 8.4 Port 6 Pin Configuration 8.5.2 Register Configuration and Description Table 8.11 shows the port 6 register configuration. Table 8.11 Port 6 Registers Name Port data register 6 Port control register 6 Port pull-up control register 6 Abbrev. PDR6 PCR6 PUCR6 R/W R/W W R/W Initial Value H'00 H'00 H'00 Address H'FFD9 H'FFE9 H'FF9F 138 Port Data Register 6 (PDR6) Bit 7 P67 Initial value Read/Write 0 R/W 6 P66 0 R/W 5 P65 0 R/W 4 P64 0 R/W 3 P63 0 R/W 2 P62 0 R/W 1 P61 0 R/W 0 P60 0 R/W PDR6 is an 8-bit register that stores data for port 6 pins P67 to P60. If port 6 is read while PCR6 bits are set to 1, the values stored in PDR6 are directly read, regardless of the actual pin states. If port 6 is read while PCR6 bits are cleared to 0, the pin states are read. Upon reset, PDR6 is initialized to H'00. Port Control Register 6 (PCR6) Bit 7 PCR67 Initial value Read/Write 0 W 6 PCR66 0 W 5 PCR65 0 W 4 PCR64 0 W 3 PCR63 0 W 2 PCR62 0 W 1 PCR61 0 W 0 PCR60 0 W PCR6 is an 8-bit register for controlling whether each of the port 6 pins P67 to P60 functions as an input pin or output pin. Setting a PCR6 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. Upon reset, PCR6 is initialized to H'00. PCR6 is a write-only register. All bits are read as 1. Port Pull-Up Control Register 6 (PUCR6) Bit 7 6 5 4 3 2 1 0 PUCR67 PUCR66 PUCR65 PUCR64 PUCR63 PUCR62 PUCR61 PUCR60 Initial value Read/Write 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W PUCR6 controls whether the MOS pull-up of each port 6 pin is on or off. When a PCR6 bit is cleared to 0, setting the corresponding PUCR6 bit to 1 turns on the MOS pull-up for the corresponding pin, while clearing the bit to 0 turns off the MOS pull-up. Upon reset, PUCR6 is initialized to H'00. 139 8.5.3 Pin Functions Table 8.12 shows the port 6 pin functions. Table 8.12 Port 6 Pin Functions Pin P67 to P6 0 Pin Functions and Selection Method The pin function depends on bit PCR6n in PCR6. (n = 7 to 0) PCR6n Pin function 0 P6n input pin 1 P6n output pin 8.5.4 Pin States Table 8.13 shows the port 6 pin states in each operating mode. Table 8.13 Port 6 Pin States Pins P67 to P6 0 Reset Sleep Subsleep Standby Watch Subactive Active HighRetains Retains impedance previous previous state state HighRetains Functional Functional impedance* previous state Note: * A high-level signal is output when the MOS pull-up is in the on state. 8.5.5 MOS Input Pull-Up Port 6 has a built-in MOS input pull-up function that can be controlled by software. When a PCR6 bit is cleared to 0, setting the corresponding PUCR6 bit to 1 turns on the MOS pull-up for that pin. The MOS pull-up function is in the off state after a reset. PCR6n PUC6n MOS input pull-up Note: * Don't care (n = 7 to 0) 0 Off 0 1 On 1 * Off 140 8.6 8.6.1 Port 7 Overview Port 7 is an 8-bit I/O port, configured as shown in figure 8.5. P7 7 P7 6 P7 5 Port 7 P7 4 P7 3 P7 2 P7 1 P7 0 Figure 8.5 Port 7 Pin Configuration 8.6.2 Register Configuration and Description Table 8.14 shows the port 7 register configuration. Table 8.14 Port 7 Registers Name Port data register 7 Port control register 7 Abbrev. PDR7 PCR7 R/W R/W W Initial Value H'00 H'00 Address H'FFDA H'FFEA 141 Port Data Register 7 (PDR7) Bit 7 P77 Initial value Read/Write 0 R/W 6 P76 0 R/W 5 P75 0 R/W 4 P74 0 R/W 3 P73 0 R/W 2 P72 0 R/W 1 P71 0 R/W 0 P70 0 R/W PDR7 is an 8-bit register that stores data for port 7 pins P77 to P70. If port 7 is read while PCR7 bits are set to 1, the values stored in PDR7 are directly read, regardless of the actual pin states. If port 7 is read while PCR7 bits are cleared to 0, the pin states are read. Upon reset, PDR7 is initialized to H'00. Port Control Register 7 (PCR7) Bit 7 PCR77 Initial value Read/Write 0 W 6 PCR76 0 W 5 PCR75 0 W 4 PCR74 0 W 3 PCR73 0 W 2 PCR72 0 W 1 PCR71 0 W 0 PCR70 0 W PCR7 is an 8-bit register for controlling whether each of the port 7 pins P77 to P70 functions as an input pin or output pin. Setting a PCR7 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. Upon reset, PCR7 is initialized to H'00. PCR7 is a write-only register. All bits are read as 1. 142 8.6.3 Pin Functions Table 8.15 shows the port 7 pin functions. Table 8.15 Port 7 Pin Functions Pin P77 to P7 0 Pin Functions and Selection Method The pin function depends on bit PCR7n in PCR7. (n = 7 to 0) PCR7n Pin function 0 P7n input pin 1 P7n output pin 8.6.4 Pin States Table 8.16 shows the port 7 pin states in each operating mode. Table 8.16 Port 7 Pin States Pins P77 to P7 0 Reset Sleep Subsleep Standby Highimpedance Watch Subactive Active HighRetains Retains impedance previous previous state state Retains Functional Functional previous state 143 8.7 8.7.1 Port 8 Overview Port 8 is an 8-bit I/O port configured as shown in figure 8.6. P8 7 P8 6 P8 5 Port 8 P8 4 P8 3 P8 2 P8 1 P8 0 Figure 8.6 Port 8 Pin Configuration 8.7.2 Register Configuration and Description Table 8.17 shows the port 8 register configuration. Table 8.17 Port 8 Registers Name Port data register 8 Port control register 8 Abbrev. PDR8 PCR8 R/W R/W W Initial Value H'00 H'00 Address H'FFDB H'FFEB 144 Port Data Register 8 (PDR8) Bit 7 P87 Initial value Read/Write 0 R/W 6 P86 0 R/W 5 P85 0 R/W 4 P84 0 R/W 3 P83 0 R/W 2 P82 0 R/W 1 P81 0 R/W 0 P80 0 R/W PDR8 is an 8-bit register that stores data for port 8 pins P87 to P80. If port 8 is read while PCR8 bits are set to 1, the values stored in PDR8 are directly read, regardless of the actual pin states. If port 8 is read while PCR8 bits are cleared to 0, the pin states are read. Upon reset, PDR8 is initialized to H'00. Port Control Register 8 (PCR8) Bit 7 PCR87 Initial value Read/Write 0 W 6 PCR86 0 W 5 PCR85 0 W 4 PCR84 0 W 3 PCR83 0 W 2 PCR82 0 W 1 PCR81 0 W 0 PCR80 0 W PCR8 is an 8-bit register for controlling whether each of the port 8 pins P87 to P80 functions as an input or output pin. Setting a PCR8 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. Upon reset, PCR8 is initialized to H'00. PCR8 is a write-only register. All bits are read as 1. 145 8.7.3 Pin Functions Table 8.18 gives the port 8 pin functions. Table 8.18 Port 8 Pin Functions Pin P87 to P8 0 Pin Functions and Selection Method The pin function depends on bit PCR8n in PCR8. (n = 7 to 0) PCR8n Pin function 0 P8n input pin 1 P8n output pin 8.7.4 Pin States Table 8.19 shows the port 8 pin states in each operating mode. Table 8.19 Port 8 Pin States Pins P87 to P8 0 Reset Sleep Subsleep Standby Highimpedance Watch Subactive Active HighRetains Retains impedance previous previous state state Retains Functional Functional previous state 146 8.8 8.8.1 Port A Overview Port A is a 3-bit I/O port configured as shown in figure 8.7. PA 3 Port A PA 2 PA 1 Figure 8.7 Port A Pin Configuration 8.8.2 Register Configuration and Description Table 8.20 shows the port A register configuration. Table 8.20 Port A Registers Name Port data register A Port control register A Abbrev. PDRA PCRA R/W R/W W Initial Value H'F0 H'F1 Address H'FFDD H'FFED 147 Port Data Register A (PDRA) Bit 7 -- Initial value Read/Write 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 PA3 0 R/W 2 PA2 0 R/W 1 PA1 0 R/W 0 -- 0 -- PDRA is an 8-bit register that stores data for port A pins PA3 to PA 1. If port A is read while PCRA bits are set to 1, the values stored in PDRA are directly read, regardless of the actual pin states. If port A is read while PCRA bits are cleared to 0, the pin states are read. Upon reset, PDRA is initialized to H'F0. Port Control Register A (PCRA) Bit 7 -- Initial value Read/Write 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 PCRA3 0 W 2 PCRA2 0 W 1 PCRA1 0 W 0 -- 1 -- PCRA is an 8-bit register for controlling whether each of the port A pins PA3 to PA1 functions as an input or output pin. Setting a PCRA bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin. Upon reset, PCRA is initialized to H'F1. PCRA is a write-only register. All bits are read as 1. 148 8.8.3 Pin Functions Table 8.21 gives the port A pin functions. Table 8.21 Port A Pin Functions Pin PA3 to PA 1 Pin Functions and Selection Method The pin function depends on bit PCRAn in PCRA. (n = 3 to 1) PCRAn Pin function 0 PAn input pin 1 PAn output pin 8.8.4 Pin States Table 8.22 shows the port A pin states in each operating mode. Table 8.22 Port A Pin States Pins PA3 to PA 1 Reset Sleep Subsleep Standby Highimpedance Watch Subactive Active HighRetains Retains impedance previous previous state state Retains Functional Functional previous state 149 8.9 8.9.1 Port B Overview Port B is an 2-bit input-only port configured as shown in figure 8.8. Port B PB7 /AN 7 PB6 /AN 6 Figure 8.8 Port B Pin Configuration 8.9.2 Register Configuration and Description Table 8.23 shows the port B register configuration. Table 8.23 Port B Register Name Port data register B Abbrev. PDRB R/W R Address H'FFDE Port Data Register B (PDRB) Bit 7 PB7 Read/Write R 6 PB6 R 5 -- -- 4 -- -- 3 -- -- 2 -- -- 1 -- -- 0 -- -- Reading PDRB always gives the pin states. However, if a port B pin is selected as an analog input channel for the A/D converter by AMR bits CH3 to CH0, that pin reads 0 regardless of the input voltage. 150 Section 9 Timers 9.1 Overview The H8/3627 Series provides three timers (timers A, F, and G) on-chip. Table 9.1 outlines the functions of timers A, F, and G. Table 9.1 Name Timer A Timer Functions Functions 8-bit timer Internal Clock Event Input Pin -- Waveform Output Pin -- -- Remarks Interval timer o/8 to o/8192 (8 choices) Time base oW/128 -- (choice of 4 overflow periods) o/4 to o/32, oW/4 to o W /32 (8 choices) o/2 to o/32 (4 choices) -- Clock output TMOW Timer F * 16-bit free-running timer * Event counter * Can be used as two independent 8-bit timers * Output compare * 8-bit timer * Input capture * Interval timer TMIF TMOFL TMOFH Timer G o/2 to o/64, oW/2 (4 choices) TMIG -- * Counter clear designation possible * Built-in noise canceller circuit for input capture 151 9.2 9.2.1 Timer A Overview Timer A is an 8-bit timer with interval timing and real-time clock time-base functions. The clock time-base function is available when a 32.768-kHz crystal oscillator is connected. A clock signal divided from 32.768 kHz or from the system clock can be output at the TMOW pin. Features: Features of timer A are given below. * Choice of eight internal clock sources (o/8192, o/4096, o/2048, o/512, o/256, o/128, o/32, o/8). * Choice of four overflow periods (1 s, 0.5 s, 0.25 s, 31.25 ms) when timer A is used as a clock time base (using a 32.768 kHz crystal oscillator). * An interrupt is requested when the counter overflows. * Any of eight clock signals can be output from pin TMOW: 32.768 kHz divided by 32, 16, 8, or 4 (1 kHz, 2 kHz, 4 kHz, 8 kHz), or the system clock divided by 32, 16, 8, or 4. Block Diagram: Figure 9.1 shows a block diagram of timer A. oW 1/4 oW/4 PSW TMA oW /128 TCA TMOW o/32 o/16 o/8 o/4 o / 8* / 64 * /128 * o/8192, o/4096, o/2048, o/512, o/256, o/128, o/32, o/8 PSS /256 * IRRTA Legend: TMA: Timer mode register A TCA: Timer counter A IRRTA: Timer A overflow interrupt request flag PSW: Prescaler W PSS: Prescaler S Note: Can be selected only when the prescaler W output (o W /128) is used as the TCA input clock. Figure 9.1 Block Diagram of Timer A 152 Internal data bus oW /32 oW /16 oW /8 oW /4 Pin Configuration: Table 9.2 shows the timer A pin configuration. Table 9.2 Name Clock output Pin Configuration Abbrev. TMOW I/O Output Function Output of waveform generated by timer A output circuit Register Configuration: Table 9.3 shows the register configuration of timer A. Table 9.3 Name Timer mode register A Timer counter A Timer A Registers Abbrev. TMA TCA R/W R/W R Initial Value H'10 H'00 Address H'FFB0 H'FFB1 9.2.2 Register Descriptions Timer Mode Register A (TMA) Bit 7 TMA7 Initial value Read/Write 0 R/W 6 TMA6 0 R/W 5 TMA5 0 R/W 4 -- 1 -- 3 TMA3 0 R/W 2 TMA2 0 R/W 1 TMA1 0 R/W 0 TMA0 0 R/W TMA is an 8-bit read/write register for selecting the prescaler, input clock, and output clock. Upon reset, TMA is initialized to H'10. Bits 7 to 5--Clock Output Select (TMA7 to TMA5): Bits 7 to 5 choose which of eight clock signals is output at the TMOW pin. The system clock divided by 32, 16, 8, or 4 can be output in active mode and sleep mode. A 32.768 kHz signal divided by 32, 16, 8, or 4 can be output in active mode, sleep mode, and subactive mode. 153 Bit 7: TMA7 0 Bit 6: TMA6 0 Bit 5: TMA5 0 1 Clock Output o/32 o/16 o/8 o/4 oW/32 oW/16 oW/8 oW/4 (initial value) 1 0 1 1 0 0 1 1 0 1 Bit 4--Reserved Bit: Bit 4 is reserved; it is always read as 1, and cannot be modified. Bits 3 to 0--Internal Clock Select (TMA3 to TMA0): Bits 3 to 0 select the clock input to TCA. The selection is made as follows. Description Bit 3: TMA3 0 Bit 2: TMA2 0 Bit 1: TMA1 0 Bit 0: TMA0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Prescaler and Divider Ratio or Overflow Period PSS, o/8192 PSS, o/4096 PSS, o/2048 PSS, o/512 PSS, o/256 PSS, o/128 PSS, o/32 PSS, o/8 PSW, 1 s PSW, 0.5 s PSW, 0.25 s PSW, 0.03125 s PSW and TCA are reset Clock time base (initial value) Function Interval timer 154 Timer Counter A (TCA) Bit 7 TCA7 Initial value Read/Write 0 R 6 TCA6 0 R 5 TCA5 0 R 4 TCA4 0 R 3 TCA3 0 R 2 TCA2 0 R 1 TCA1 0 R 0 TCA0 0 R TCA is an 8-bit read-only up-counter, which is incremented by internal clock input. The clock source for input to this counter is selected by bits TMA3 to TMA0 in timer mode register A (TMA). TCA values can be read by the CPU in active mode, but cannot be read in subactive mode. When TCA overflows, the IRRTA bit in interrupt request register 1 (IRR1) is set to 1. TCA is cleared by setting bits TMA3 and TMA2 of TMA to 11. Upon reset, TCA is initialized to H'00. 9.2.3 Timer Operation Interval Timer Operation: When bit TMA3 in timer mode register A (TMA) is cleared to 0, timer A functions as an 8-bit interval timer. Upon reset, TCA is cleared to H'00 and bit TMA3 is cleared to 0, so up-counting and interval timing resume immediately. The clock input to timer A is selected by bits TMA2 to TMA0 in TMA; any of eight internal clock signals output by prescaler S can be selected. After the count value in TCA reaches H'FF, the next clock signal input causes timer A to overflow, setting bit IRRTA to 1 in interrupt request register 1 (IRR1). If IENTA = 1 in interrupt enable register 1 (IENR1), a CPU interrupt is requested.* At overflow, TCA returns to H'00 and starts counting up again. In this mode timer A functions as an interval timer that generates an overflow output at intervals of 256 input clock pulses. Note: * For details on interrupts, see 3.3, Interrupts. Real-Time Clock Time Base Operation: When bit TMA3 in TMA is set to 1, timer A functions as a real-time clock time base by counting clock signals output by prescaler W. The overflow period of timer A is set by bits TMA1 and TMA0 in TMA. A choice of four periods is available. In time base operation (TMA3 = 1), setting bit TMA2 to 1 clears both TCA and prescaler W to their initial values of H'00. 155 Clock Output: Setting bit TMOW in port mode register 1 (PMR1) to 1 causes a clock signal to be output at pin TMOW. Eight different clock output signals can be selected by means of bits TMA7 to TMA5 in TMA. The system clock divided by 32, 16, 8, or 4 can be output in active mode and sleep mode. A 32.768 kHz signal divided by 32, 16, 8, or 4 can be output in active mode, sleep mode, and subactive mode. 9.2.4 Timer A Operation States Table 9.4 summarizes the timer A operation states. Table 9.4 Timer A Operation States Reset Active Reset Reset Reset Sleep Watch Subactive Halted Subsleep Halted Standby Halted Operation Mode TCA Interval Clock time base TMA Functions Functions Halted Functions Functions Functions Functions Functions Halted Functions Retained Retained Functions Retained Retained Note: When real-time clock time-base functions are selected as the internal clock of TCA in active mode or sleep mode, the internal clock is not synchronous with the system clock, so it is synchronized by a synchronizing circuit. This may result in a maximum error of 1/o (s) in the count cycle. 156 9.3 9.3.1 Timer F Overview Timer F is a 16-bit timer with an output compare function. Compare match signals can be used to reset the counter, request an interrupt, or toggle the output. Timer F can also be used for external event counting, and can operate as two independent 8-bit timers, timer FH and timer FL. Features: Features of timer F are given below. * Choice of four internal clock sources (o/32, o/16, o/4, o/2) or an external clock (can be used as an external event counter). * Output from pin TMOFH is toggled by one compare match signal (the initial value of the toggle output can be set). * Counter can be reset by the compare match signal. * Two interrupt sources: counter overflow and compare match. * Can operate as two independent 8-bit timers (timer FH and timer FL) in 8-bit mode. Timer FH 8-bit timer (clocked by timer FL overflow signals when timer F operates as a 16-bit timer). Choice of four internal clocks (o/32, o/16, o/4, o/2). Output from pin TMOFH is toggled by one compare match signal (the initial value of the toggle output can be set). Counter can be reset by the compare match signal. Two interrupt sources: counter overflow and compare match. Timer FL 8-bit timer/event counter Choice of four internal clocks (o/32, o/16, o/4, o/2) or event input at pin TMIF. Output from pin TMOFL is toggled by one compare match signal (the initial value of the toggle output can be set). Counter can be reset by the compare match signal. Two interrupt sources: counter overflow and compare match. 157 Block Diagram: Figure 9.2 shows a block diagram of timer F. o PSS IRRTFL TCRF TMIF TMOFL Toggle circuit TCFL Compare circuit Internal data bus Match IRRTFH OCRFL TCFH Toggle circuit TMOFH Compare circuit OCRFH TCSRF Legend: TCRF: TCSRF: TCFH: TCFL: OCRFH: OCRFL: IRRTFH: IRRTFL: PSS: Timer control register F Timer control status register F 8-bit timer counter FH 8-bit timer counter FL Output compare register FH Output compare register FL Timer FH interrupt request flag Timer FL interrupt request flag Prescaler S Figure 9.2 Block Diagram of Timer F 158 Pin Configuration: Table 9.5 shows the timer F pin configuration. Table 9.5 Name Timer F event input Timer FH output Timer FL output Pin Configuration Abbrev. TMIF TMOFH TMOFL I/O Input Output Output Function Event input to TCFL Timer FH toggle output Timer FL toggle output Register Configuration: Table 9.6 shows the register configuration of timer F. Table 9.6 Name Timer control register F Timer control/status register F 8-bit timer counter FH 8-bit timer counter FL Output compare register FH Output compare register FL Timer F Registers Abbrev. TCRF TCSRF TCFH TCFL OCRFH OCRFL R/W W R/W R/W R/W R/W R/W Initial Value H'00 H'00 H'00 H'00 H'FF H'FF Address H'FFB6 H'FFB7 H'FFB8 H'FFB9 H'FFBA H'FFBB 9.3.2 Register Descriptions 16-Bit Timer Counter (TCF) 8-Bit Timer Counter (TCFH) 8-Bit Timer Counter (TCFL) TCF Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W TCFH TCFL TCF is a 16-bit read/write up-counter consisting of two cascaded 8-bit timer counters, TCFH and TCFL. TCF can be used as a 16-bit counter, with TCFH as the upper 8 bits and TCFL as the lower 8 bits of the counter, or TCFH and TCFL can be used as independent 8-bit counters. 159 TCFH and TCFL can be read and written by the CPU, but in 16-bit mode, data transfer with the CPU takes place via a temporary register (TEMP). For details see 9.3.3, Interface with the CPU. Upon reset, TCFH and TCFL are each initialized to H'00. 16-Bit Mode (TCF): 16-bit mode is selected by clearing bit CKSH2 to 0 in timer control register F (TCRF). The TCF input clock is selected by TCRF bits CKSL2 to CKSL0. Timer control status register F (TCSRF) can be set so that counter TCF will be cleared by compare match. When TCF overflows from H'FFFF to H'0000, the overflow flag (OVFH) in TCSRF is set to 1. If bit OVIEH in TCSRF is set to 1 when an overflow occurs, bit IRRTFH in interrupt request register 2 (IRR2) will be set to 1; and if bit IENTFH in interrupt enable register 2 (IENR2) is set to 1, a CPU interrupt will be requested. 8-Bit Mode (TCFH, TCFL): When bit CKSH2 in timer control register F (TCRF) is set to 1, timer F functions as two separate 8-bit counters, TCFH and TCFL. The TCFH (TCFL) input clock is selected by TCRF bits CKSH2 to CKSH0 (CKSL2 to CKSL0). TCFH (TCFL) can be cleared by a compare match signal. This designation is made in bit CCLRH (CCLRL) in TCSRF. When TCFH (TCFL) overflows from H'FF to H'00, the overflow flag OVFH (OVFL) in TCSRF is set to 1. If bit OVIEH (OVIEL) in TCSRF is set to 1 when an overflow occurs, bit IRRTFH (IRRTHL) in interrupt request register 2 (IRR2) will be set to 1; and if bit IENTFH (IENTFL) in interrupt enable register 2 (IENR2) is set to 1, a CPU interrupt will be requested. 16-Bit Output Compare Register (OCRF) 8-Bit Output Compare Register (OCRFH) 8-Bit Output Compare Register (OCRFL) OCRF Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W OCRFH OCRFL OCRF is a 16-bit read/write output compare register consisting of two 8-bit read/write registers OCRFH and OCRFL. It can be used as a 16-bit output compare register, with OCRFH as the 160 upper 8 bits and OCRFL as the lower 8 bits of the register, or OCRFH and OCRFL can be used as independent 8-bit registers. OCRFH and OCRFL can be read and written by the CPU, but in 16-bit mode, data transfer with the CPU takes place via a temporary register (TEMP). For details see 9.3.3, Interface with the CPU. Upon reset, OCRFH and OCRFL are each initialized to H'FF. 16-Bit Mode (OCRF): 16-bit mode is selected by clearing bit CKSH2 to 0 in timer control register F (TCRF). The OCRF contents are always compared with the 16-bit timer counter (TCF). When the contents match, the compare match flag (CMFH) in TCSRF is set to 1. Also, IRRTFH in interrupt request register 2 (IRR2) is set to 1. If bit IENTFH in interrupt enable register 2 (IENR2) is set to 1, a CPU interrupt is requested. Output for pin TMOFH can be toggled by compare match. The output level can also be set to high or low by bit TOLH of timer control register F (TCRF). 8-Bit Mode (OCRFH, OCRFL): Setting bit CKSH2 in TCRF to 1 results in two 8-bit independent registers, OCRFH and OCRFL. The OCRFH contents are always compared with TCFH, and the OCRFL contents are always compared with TCFL. When the contents match, the compare match flag (CMFH or CMFL) in TCSRF is set to 1. Also, bit IRRTFH (IRRTFL) in interrupt request register 2 (IRR2) set to 1. If bit IENTFH (IENTFL) in interrupt enable register 2 (IENR2) is set to 1 at this time, a CPU interrupt is requested. The output at pin TMOFH (TMOFL) can be toggled by compare match. The output level can also be set to high or low by bit TOLH (TOLL) of the timer control register (TCRF). 161 Timer Control Register F (TCRF) Bit 7 TOLH Initial value Read/Write 0 W 6 CKSH2 0 W 5 CKSH1 0 W 4 CKSH0 0 W 3 TOLL 0 W 2 CKSL2 0 W 1 CKSL1 0 W 0 CKSL0 0 W TCRF is an 8-bit write-only register. It is used to switch between 16-bit mode and 8-bit mode, to select among four internal clocks and an external event, and to select the output level at pins TMOFH and TMOFL. Upon reset, TCRF is initialized to H'00. Bit 7--Toggle Output Level H (TOLH): Bit 7 sets the output level at pin TMOFH. The setting goes into effect immediately after this bit is written. Bit 7: TOLH 0 1 Description Low level High level (initial value) Bits 6 to 4--Clock Select H (CKSH2 to CKSH0): Bits 6 to 4 select the input to TCFH from four internal clock signals or the overflow of TCFL. Bit 6: CKSH2 0 1 Bit 5: CKSH1 * 0 Bit 4: CKSH0 * 0 1 1 0 1 Note: * Don't care Description 16-bit mode selected. TCFL overflow signals are counted. (initial value) Internal clock: o/32 Internal clock: o/16 Internal clock: o/4 Internal clock: o/2 Bit 3--Toggle Output Level L (TOLL): Bit 3 sets the output level at pin TMOFL. The setting goes into effect immediately after this bit is written. Bit 3: TOLL 0 1 Description Low level High level (initial value) 162 Bits 2 to 0--Clock Select L (CKSL2 to CKSL0): Bits 2 to 0 select the input to TCFL from four internal clock signals or external event input. Bit 2: CKSL2 0 1 Bit 1: CKSL1 * 0 Bit 0: CKSL0 * 0 1 1 0 1 Description External event (TMIF). Rising or falling edge is counted (see note). (initial value) Internal clock: o/32 Internal clock: o/16 Internal clock: o/4 Internal clock: o/2 *: Don't care Note: The edge of the external event signal is selected by bit IEG3 in the IRQ edge select register (IEGR). See 3.3.2, Interrupt Control Registers, for details on the IRQ edge select register. Note that switching the TMIF pin function by changing bit IRQ3 in port mode register 1 (PMR1) from 0 to 1 or from 1 to 0 while the TMIF pin is at the low level may cause the timer F counter to be incremented. Timer Control/Status Register F (TCSRF) Bit 7 OVFH Initial value Read/Write 0 R/W 6 CMFH 0 R/W 5 OVIEH 0 R/W 4 CCLRH 0 R/W 3 OVFL 0 R/W 2 CMFL 0 R/W 1 OVIEL 0 R/W 0 CCLRL 0 R/W TCSRF is an 8-bit read/write register. It is used for counter clear selection, overflow and compare match indication, and enabling of interrupts caused by timer overflow. Upon reset, TCSRF is initialized to H'00. Bit 7--Timer Overflow Flag H (OVFH): Bit 7 is a status flag indicating TCFH overflow (H'FF to H'00). This flag is set by hardware and cleared by software. It cannot be set by software. Bit 7: OVFH 0 1 Description [Clearing conditions] After reading OVFH = 1, cleared by writing 0 to OVFH [Setting conditions] Set when the value of TCFH goes from H'FF to H'00 (initial value) 163 Bit 6--Compare Match Flag H (CMFH): Bit 6 is a status flag indicating a compare match between TCFH and OCRFH. This flag is set by hardware and cleared by software. It cannot be set by software. Bit 6: CMFH 0 1 Description [Clearing conditions] After reading CMFH = 1, cleared by writing 0 to CMFH [Setting conditions] Set when the TCFH value matches OCRFH value (initial value) Bit 5--Timer Overflow Interrupt Enable H (OVIEH): Bit 5 enables or disables TCFH overflow interrupts. Bit 5: OVIEH 0 1 Description TCFH overflow interrupt disabled TCFH overflow interrupt enabled (initial value) Bit 4--Counter Clear H (CCLRH): In 16-bit mode, bit 4 selects whether or not TCF is cleared when a compare match occurs between TCF and OCRF. In 8-bit mode, bit 4 selects whether or not TCFH is cleared when a compare match occurs between TCFH and OCRFH. Bit 4: CCLRH 0 Description 16-bit mode: TCF clearing by compare match disabled 8-bit mode: TCFH clearing by compare match disabled 1 16-bit mode: TCF clearing by compare match enabled 8-bit mode: TCFH clearing by compare match enabled (initial value) Bit 3--Timer Overflow Flag L (OVFL): Bit 3 is a status flag indicating TCFL overflow (H'FF to H'00). This flag is set by hardware and cleared by software. It cannot be set by software. Bit 3: OVFL 0 1 Description [Clearing conditions] After reading OVFL = 1, cleared by writing 0 to OVFL [Setting conditions] Set when the value of TCFL goes from H'FF to H'00 (initial value) 164 Bit 2--Compare Match Flag L (CMFL): Bit 2 is a status flag indicating a compare match between TCFL and OCRFL. This flag is set by hardware and cleared by software. It cannot be set by software. Bit 2: CMFL 0 1 Description [Clearing conditions] After reading CMFL = 1, cleared by writing 0 to CMFL [Setting conditions] Set when the TCFL value matches the OCRFL value (initial value) Bit 1--Timer Overflow Interrupt Enable L (OVIEL): Bit 1 enables or disables TCFL overflow interrupts. Bit 1: OVIEL 0 1 Description TCFL overflow interrupt disabled TCFL overflow interrupt enabled (initial value) Bit 0--Counter Clear L (CCLRL): Bit 0 selects whether or not TCFL is cleared when a compare match occurs between TCFL and OCRFL. Bit 0: CCLRL 0 1 Description TCFL clearing by compare match disabled TCFL clearing by compare match enabled (initial value) 165 9.3.3 Interface with the CPU TCF and OCRF are 16-bit read/write registers, whereas the data bus between the CPU and on-chip peripheral modules has an 8-bit width. For this reason, when the CPU accesses TCF or OCRF, it makes use of an 8-bit temporary register (TEMP). In 16-bit mode, when reading or writing TCF or writing OCRF, always use two consecutive byte size MOV instructions, and always access the upper byte first. Data will not be transferred properly if only the upper byte or only the lower byte is accessed. In 8-bit mode there is no such restriction on the order of access. Write Access: When the upper byte is written, the upper-byte data is loaded into the TEMP register. Next when the lower byte is written, the data in TEMP goes to the upper byte of the register, and the lower-byte data goes directly to the lower byte of the register. Figure 9.3 shows a TCF write operation when H'AA55 is written to TCF. Read Access: When the upper byte of TCF is read, the upper-byte data is sent directly to the CPU, and the lower byte is loaded into TEMP. Next when the lower byte is read, the lower byte in TEMP is sent to the CPU. When the upper byte of OCRF is read, the upper-byte data is sent directly to the CPU. Next when the lower byte is read, the lower-byte data is sent directly to the CPU. Figure 9.4 shows a TCF read operation when H'AAFF is read from TCF. 166 When writing the upper byte CPU [H'AA] Bus interface Internal data bus TEMP [H'AA] TCFH [ ] When writing the lower byte TCFL [ ] CPU [H'55] Bus interface Internal data bus TEMP [H'AA] TCFH [H'AA] TCFL [H'55] Figure 9.3 TCF Write Operation (CPU TCF) 167 When reading the upper byte CPU [H'AA] Bus interface Internal data bus TEMP (H'FF) TCFH [H'AA] When reading the lower byte TCFL [H'FF] CPU [H'FF] Bus interface Internal data bus TEMP [H'FF] TCFH [AB] * TCFL [00] * Note: * Becomes H'AB00 if counter is incremented once. Figure 9.4 TCF Read Operation (TCF CPU) 168 9.3.4 Timer Operation Timer F is a 16-bit timer/counter that increments with each input clock. When the value set in output compare register F matches the count in timer F, the timer can be cleared, an interrupt can be requested, and the port output can be toggled. Timer F can also be used as two independent 8-bit timers. Timer F Operation: Timer F can operate in either 16-bit timer mode or 8-bit timer mode. These modes are described below. * 16-bit timer mode Timer F operates in 16-bit timer mode when the CKSH2 bit in timer control register F (TCRF) is cleared to 0. A reset initializes timer counter F (TCF) to H'0000, output compare register F (OCRF) to H'FFFF, and timer control register F (TCRF) and timer control status register F (TCSRF) to H'00. Timer F begins counting external event input signals (TMIF). The edge of the external event signal is selected by the IEG3 bit in the IRQ edge select register (IEGR). The operational clock of timer F can be selected by setting bits CSKL2 through CKSL0 in TCRF, from four internal clocks output from prescaler S as well as from an external clock. TCF is continuously compared with the contents of OCRF. When these two values match, the CMFH bit in TCSRF is set to 1. At this time if IENTFH of IENR2 is 1, a CPU interrupt is requested and the output at pin TMOFH is toggled. If the CCLRH bit in TCSRF is 1, TCF is cleared. The output at pin TMOFH can also be set by the TOLH bit in TCRF. If timer F overflows (from H'FFFF to H'0000), the OVFH bit in TCSRF is set to 1. At this time, if the OVIEH bit in TCSRF and the IENTFH bit in IENR2 are both 1, CPU interrupt is requested. * 8-bit timer mode When the CKSH2 bit in TCRF is set to 1, timer F operates as two independent 8-bit timers, TCFH and TCFL. The input clock of TCFH/TCFL is selected by bits CKSH2 to CKSH0/CKSL2 to CKSL0 in TCRF. When TCFH/TCFL and the contents of OCRFH/OCRFL match, the CMFH/CMFL bit in TCSRF is set to 1. If the IENTFH/IENTFL bit in IENR2 is 1, a CPU interrupt is requested and the output at pin TMOFH/TMOFL is toggled. If the CCLRH/CCLRL bit in TCRF is 1, TCFH/TCFL is cleared. The output at pin TMOFH/TMOFL can also be set by the TOLH/TOLL bit in TCRF. When TCFH/TCFL overflows from H'FF to H'00, the OVFH/OVFL bit in TCSRF is set to 1. At this time, if the OVIEH/OVIEL bit in TCSRF and the IENTFH/IENTFL bit in IENR2 are both 1, a CPU interrupt is requested. 169 TCF Count Timing: TCF is incremented by each pulse of the input clock (internal clock or external event). * Internal clock The settings of bits CKSH2 to CKSH0 or bits CKSL2 to CKSL0 in TCRF select one of four internal clock signals (o/32, o/16, o/4, or o/2) divided from the system clock (o). * External event External event input is selected by clearing bit CKSL2 to 0 in TCRF. Either rising or falling edges of the clock input can be counted. The edge is selected by bit IEG3 in IEGR. An external clock pulse width of at least two system clock cycles (o) is necessary; otherwise the counter will not operate properly. TMOFH and TMOFL Output Timing: The outputs at pins TMOFH and TMOFL are the values set in bits TOLH and TOLL in TCRF. When a compare match occurs, the output value is inverted. Figure 9.5 shows the output timing. o TMIF (when IEG3 = 1) Count input clock TCF N N+1 N N+1 OCRF N N Compare match signal TMOFH, TMOFL Figure 9.5 TMOFH, TMOFL Output Timing TCF Clear Timing: TCF can be cleared at compare match with OCRF. Timer Overflow Flag (OVF) Set Timing: OVF is set to 1 when TCF overflows (goes from H'FFFF to H'0000). 170 Compare Match Flag Set Timing: The compare match flags (CMFH or CMFL) are set to 1 when a compare match occurs between TCF and OCRF. A compare match signal is generated in the final state in which the values match (when TCF changes from the matching count value to the next value). When TCF and OCRF match, a compare match signal is not generated until the next counter clock pulse. Timer F Operation States: Table 9.7 summarizes the timer F operation states. Table 9.7 Timer F Operation States Reset Reset Reset Reset Reset Active Functions Functions Functions Functions Sleep Functions Retained Retained Retained Watch Halted Retained Retained Retained Subactive Halted Subsleep Halted Standby Halted Operation Mode TCF OCRF TCRF TCSRF Retained Retained Retained Retained Retained Retained Retained Retained Retained 9.3.5 Application Notes The following conflicts can arise in timer F operation. 16-Bit Timer Mode: The output at pin TMOFH toggles when all 16 bits match and a compare match signal is generated. If the compare match signal occurs at the same time as new data is written in TCRF by a MOV instruction, however, the new value written in bit TOLH will be output at pin TMOFH. The TMOFL output in 16-bit mode is indeterminate, so this output should not be used. Use the pin as a general input or output port. If an OCRFL write occurs at the same time as a compare match signal, the compare match signal is inhibited. If a compare match occurs between the written data and the counter value, however, a compare match signal will be generated at that point. The compare match signal is output in synchronization with the TCFL clock, so if this clock is stopped no compare match signal will be generated, even if a compare match occurs. Compare match flag CMFH is set when all 16 bits match and a compare match signal is generated; bit CMFL is set when the setting conditions are met for the lower 8 bits. The overflow flag (OVFH) is set when TCF overflows; bit OVFL is set if the setting conditions are met when the lower 8 bits overflow. If a write to TCFL occurs at the same time as an overflow signal, the overflow signal is not output. 171 8-Bit Timer Mode * TCFH and OCRFH The output at pin TMOFH toggles when there is a compare match. If the compare match signal occurs at the same time as new data is written in TCRF by a MOV instruction, however, the new value written in bit TOLH will be output at pin TMOFH. If an OCRFH write occurs at the same time as a compare match signal, the compare match signal is inhibited. If a compare match occurs between the written data and the counter value, however, a compare match signal will be generated at that point. The compare match signal is output in synchronization with the TCFH clock. If a TCFH write occurs at the same time as an overflow signal, the overflow signal is not output. * TCFL and OCRFL The output at pin TMOFL toggles when there is a compare match. If the compare match signal occurs at the same time as new data is written in TCRF by a MOV instruction, however, the new value written in bit TOLL will be output at pin TMOFL. If an OCRFL write occurs at the same time as a compare match signal, the compare match signal is inhibited. If a compare match occurs between the written data and the counter value, however, a compare match signal will be generated at that point. The compare match signal is output in synchronization with the TCFL clock, so if this clock is stopped no compare match signal will be generated, even if a compare match occurs. If a TCFL write occurs at the same time as an overflow signal, the overflow signal is not output. 172 9.4 9.4.1 Timer G Overview Timer G is an 8-bit timer, with input capture/interval functions for separately capturing the rising edge and falling edge of pulses input at the input capture pin (input capture input signal). Timer G has a built-in noise canceller circuit that can eliminate high-frequency noise from the input capture signal, enabling accurate measurement of its duty cycle. When timer G is not used for input capture, it functions as an 8-bit interval timer. Features: Features of timer G are given below. * Choice of four internal clock sources (o/64, o/32, o/2, oW/2) * Input capture function Separate input capture functions are provided for the rising and falling edges. * Counter overflow detection Can detect whether overflow occurred when the input capture signal was high or low. * Choice of counter clear It is possible to select whether or not the counter is cleared at the rising edge, falling edge, or both edges of the input capture input signal. * Two interrupt sources There is one input capture interrupt source and one overflow interrupt source. For input capture, the rising or falling edge can be selected. * Built-in noise-canceller circuit The noise canceller circuit can eliminate high-frequency noise in the input capture signal. * Operates in subactive and subsleep modes When oW/2 is selected as the internal clock source, timer G can operate in the subactive and subsleep modes. 173 Block Diagram: Figure 9.6 shows a block diagram of timer G. o PSS TMG Level sense circuit ICRGF Internal data bus IRRTG Legend: TMG: TCG: ICRGF: ICRGR: IRRTG: NCS: PSS: o W /2 TMIG Noise canceller circuit Edge sense circuit TCG NCS ICRGR Timer mode register G Timer counter G Input capture register GF Input capture register GR Timer G interrupt request flag Noise canceller select Prescaler S Figure 9.6 Block Diagram of Timer G Pin Configuration: Table 9.8 shows the timer G pin configuration. Table 9.8 Name Input capture input Pin Configuration Abbrev. TMIG I/O Input Function Input capture 174 Register Configuration: Table 9.9 shows the register configuration of timer G. Table 9.9 Name Timer mode register G Timer counter G Input capture register GF Input capture register GR Timer G Registers Abbrev. TMG TCG ICRGF ICRGR R/W R/W -- R R Initial Value H'00 H'00 H'00 H'00 Address H'FFBC -- H'FFBD H'FFBE 9.4.2 Register Descriptions Timer Counter G (TCG) Bit 7 TCG7 Initial value Read/Write 0 -- 6 TCG6 0 -- 5 TCG5 0 -- 4 TCG4 0 -- 3 TCG3 0 -- 2 TCG2 0 -- 1 TCG1 0 -- 0 TCG0 0 -- Timer counter G (TCG) is an 8-bit up-counter which is incremented by an input clock. The input clock signal is selected by bits CKS1 and CKS0 in timer mode register G (TMG). To use TCG as an input capture timer, set bit TMIG to 1 in PMR1; to use TCG as an interval timer, clear bit TMIG to 0.* When TCG is used as an input capture timer, the TCG value can be cleared at the rising edge, falling edge, or both edges of the input capture signal, depending on settings in TMG. When TCG overflows (goes from H'FF to H'00), if the timer overflow interrupt enable bit (OVIE) is set to 1 in TMG, bit IRRTG in interrupt request register 2 (IRR2) is set to 1. If in addition bit IENTG in interrupt enable register 2 (IENR2) is set to 1, a CPU interrupt is requested. Details on interrupts are given in 3.3, Interrupts. TCG cannot be read or written by the CPU. Upon reset, TCG is initialized to H'00. Note: * An input capture signal may be generated when TMIG is rewritten. 175 Input Capture Register GF (ICRGF) Bit 7 6 5 4 3 2 1 0 ICRGF7 ICRGF6 ICRGF5 ICRGF4 ICRGF3 ICRGF2 ICRGF1 ICRGF0 Initial value Read/Write 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R ICRGF is an 8-bit read-only register. When the falling edge of the input capture signal is detected, the TCG value at that time is transferred to ICRGF. If the input capture interrupt select bit (IIEGS) is set to 1 in TMG, bit IRRTG in interrupt request register 2 (IRR2) is set to 1. If in addition bit IENTG in interrupt enable register 2 (IENR2) is set to 1, a CPU interrupt is requested. Details on interrupts are given in 3.3, Interrupts. To ensure proper input capture when the noise canceller is not used, the pulse width of the input capture signal should be at least 2o or 2oSUB. Upon reset, ICRGF is initialized to H'00. Input Capture Register GR (ICRGR) Bit 7 6 5 4 3 2 1 0 ICRGR7 ICRGR6 ICRGR5 ICRGR4 ICRGR3 ICRGR2 ICRGR1 ICRGR0 Initial value Read/Write 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R ICRGR is an 8-bit read-only register. When the rising edge of the input capture signal is detected, the TCG value at that time is sent to ICRGR. If the IIEGS bit is cleared to 0 in TMG, bit IRRTG in interrupt request register 2 (IRR2) is set to 1. If in addition bit IENTG in interrupt enable register 2 (IENR2) is set to 1, a CPU interrupt is requested. Details on interrupts are given in 3.3, Interrupts. To ensure proper input capture when the noise canceller is not used, the pulse width of the input capture signal should be at least 2o or 2oSUB. Upon reset, ICRGR is initialized to H'00. 176 Timer Mode Register G (TMG) Bit 7 OVFH Initial value Read/Write 0 R/W* 6 OVFL 0 R/W* 5 OVIE 0 R/W 4 IIEGS 0 R/W 3 CCLR1 0 R/W 2 CCLR0 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W Note: * Only 0 can be written, to clear flag. TMG is an 8-bit read/write register. It controls the choice of four internal clocks, counter clear selection, and edge selection for input capture interrupt requests. It also indicates overflow status and enables or disables overflow interrupt requests. Upon reset, TMG is initialized to H'00. Bit 7--Timer Overflow Flag H (OVFH): Bit 7 is a status flag indicating that TCG overflowed (from H'FF to H'00) when the input capture signal was high. This flag is set by hardware and cleared by software. It cannot be set by software. Bit 7: OVFH 0 1 Description [Clearing conditions] After reading OVFH = 1, cleared by writing 0 to OVFH [Setting conditions] Set when the value of TCG overflows from H'FF to H'00 (initial value) Bit 6--Timer Overflow Flag L (OVFL): Bit 6 is a status flag indicating that TCG overflowed (from H'FF to H'00) when the input capture signal was low, or in interval timer operation. This flag is set by hardware and cleared by software. It cannot be set by software. Bit 6: OVFL 0 1 Description [Clearing conditions] After reading OVFL = 1, cleared by writing 0 to OVFL [Setting conditions] Set when the value of TCG overflows from H'FF to H'00 (initial value) Bit 5--Timer Overflow Interrupt Enable (OVIE): Bit 5 enables or disables TCG overflow interrupts. Bit 5: OVIE 0 1 Description TCG overflow interrupt disabled TCG overflow interrupt enabled (initial value) 177 Bit 4--Input Capture Interrupt Edge Select (IIEGS): Bit 4 selects the input signal edge at which input capture interrupts are requested. Bit 4: IIEGS 0 1 Description Interrupts are requested at the rising edge of the input capture signal (initial value) Interrupts are requested at the falling edge of the input capture signal Bits 3, 2--Counter Clear 1, 0 (CCLR1, CCLR0): Bits 3 and 2 designate whether TCG is cleared at the rising, falling, or both edges of the input capture signal, or is not cleared. Bit 3: CCLR1 0 Bit 2: CCLR0 0 1 1 0 1 Description TCG is not cleared (initial value) TCG is cleared at the falling edge of the input capture signal TCG is cleared at the rising edge of the input capture signal TCG is cleared at both edges of the input capture signal Bits 1, 0--Clock Select (CKS1, CKS0): Bits 1 and 0 select the clock input to TCG from four internal clock signals. Bit 1: CKS1 0 Bit 0: CKS0 0 1 1 0 1 Description Internal clock: o/64 Internal clock: o/32 Internal clock: o/2 Internal clock: o W /2 (initial value) 178 9.4.3 Noise Canceller Circuit The noise canceller circuit built into the H8/3637 Series is a digital low-pass filter that rejects high-frequency pulse noise in the input at the input capture pin. The noise canceller circuit is enabled by the noise canceller select (NCS)* bit in port mode register 2 (PMR2). Figure 9.7 shows a block diagram of the noise canceller circuit. Sampling clock Input capture signal C DQ latch C DQ latch C DQ latch C DQ latch C DQ latch Match detection circuit Noise canceller output t Sampling clock t: Selected by bits CKS1, CKS0. Figure 9.7 Block Diagram of Noise Canceller Circuit The noise canceller consists of five latch circuits connected in series, and a match detection circuit. When the noise canceller function is disabled (NCS = 0), the system clock is selected as the sampling clock. When the noise canceller is enabled (NCS = 1), the internal clock selected by bits CKS1 and CKS0 in TMG becomes the sampling clock. The input signal is sampled at the rising edge of this clock pulse. Data is considered correct when the outputs of all five latch circuits match. If they do not match, the previous value is retained. Upon reset, the noise canceller output is initialized after the falling edge of the input capture signal has been sampled five times. Accordingly, after the noise canceller function is enabled, pulses that have a pulse width five times greater than the sampling clock will be recognized as input capture signals. If the noise canceller circuit is not used, the input capture signal pulse width must be at least 2o or 2oSUB in order to ensure proper input capture operation. Note: Rewriting the NCS bit may cause an internal input capture signal to be generated. 179 Figure 9.8 shows a typical timing diagram for the noise canceller circuit. In this example, a highlevel input at the input capture pin is rejected as noise because its pulse width is less than five sampling clock o cycles. Input capture input signal Sampling clock Noise canceller output Rejected as noise Figure 9.8 Noise Canceller Circuit Timing (Example) 9.4.4 Timer Operation Timer G Functions: Timer G is an 8-bit up-counter that functions as an input capture timer or an interval timer. These two functions are described below. * Input capture timer operation Timer G functions as an input capture timer when bit TMIG of port mode register 1 (PMR1) is set to 1.* At reset, timer mode register G (TMG), timer counter G (TCG), input capture register GF (ICRGF), and input capture register GR (ICRGR) are all initialized to H'00. Immediately after reset, TCG begins counting an internal clock with a frequency of o divided by 64 (o/64). The clock to be input can be selected by using bits CKS1 and CKS0 in TMG from four internal clock sources. At the rising edge/falling edge of the input capture signal input to pin TMIG, the value of TCG is copied into ICRGR/ICRGF. If the input edge is the same as the edge selected by the IIEGS bit of TMG, then bit IRRTG is set to 1 in IRR2. If bit IENTG is also set to 1 in IENR2, a CPU interrupt is requested. For details on interrupts, see 3.3, Interrupts. TCG can be cleared to 0 at the rising edge, falling edge, or both edges of the input capture signal as determined with bits CCLR1 and CCLR0 of TMG. If TCG overflows while the input capture signal is high, bit OVFH of TMG is set. If TCG overflows while the input capture signal is low, bit OVFL of TMG is set. When either of these bits is set, if bit OVIE of TMG is currently set to 1, then bit IRRTG is set to 1 in IRR2. If bit IENTG is also set to 1 in IENR2, then timer G requests a CPU interrupt. For further details see 3.3, Interrupts. 180 Timer G has a noise canceller circuit that rejects high-frequency pulse noise in the input to pin TMIG. See 9.4.3, Noise Canceller Circuit, for details. Note: * Rewriting the TMIG bit may cause an internal input capture signal to be generated. * Interval timer operation Timer G functions as an interval timer when bit TMIG is cleared to 0 in PMR1. Following a reset, TCG starts counting cycles of the o/64 internal clock. This is one of four internal clock sources that can be selected by bits CKS1 and CKS0 of TMG. TCG counts up according to the selected clock source. When it overflows from H'FF to H'00, bit OVFL of TMG is set to 1. If bit OVIE of TMG is currently set to 1, then bit IRRTG is set to 1 in IRR2. If bit IENTG is also set to 1 in IENR2, then timer G requests a CPU interrupt. For further details see 3.3, Interrupts. Count Timing: TCG is incremented by input pulses from an internal clock. TMG bits CKS1 and CKS0 select one of four internal clocks (o/64, o/32, o/2, oW /2) derived by dividing the system clock (o) and the watch clock (oW ). Timing of Internal Input Capture Signals: * Timing with noise canceller function disabled Separate internal input capture signals are generated from the rising and falling edges of the external input signal. Figure 9.9 shows the timing of these signals. External input capture signal Internal input capture signal F Internal input capture signal R Figure 9.9 Input Capture Signal Timing (Noise Canceller Function Disabled) 181 * Timing with noise canceller function enabled When input capture noise cancelling is enabled, the external input capture signal is routed via the noise canceller circuit, so the internal signals are delayed from the input edge by five sampling clock cycles. Figure 9.10 shows the timing. External input capture signal Sampling clock Noise canceller circuit output Internal input capture signal R Figure 9.10 Input Capture Signal Timing (Noise Canceller Function Enabled) Timing of Input Capture: Figure 9.11 shows the input capture timing in relation to the internal input capture signal. Internal input capture signal TCG N -1 N N +1 Input capture register H'XX N Figure 9.11 Input Capture Timing 182 TCG Clear Timing: TCG can be cleared at the rising edge, falling edge, or both edges of the external input capture signal. Figure 9.12 shows the timing for clearing at both edges. External input capture signal Internal input capture signal F Internal input capture signal R TCG N H'00 N H'00 Figure 9.12 TCG Clear Timing Timer G Operation States: Table 9.10 summarizes the timer G operation states. Table 9.10 Timer G Operation States Operation Mode TCG Input capture Interval ICRGF ICRGR TMG Reset Reset Reset Reset Reset Reset Active Sleep Watch Subactive Subsleep Standby Functions* Functions* Halted Functions* Functions* Retained Functions* Functions* Retained Functions* Functions* Retained Functions Retained Retained Functions/ Functions/ Halted Halted* Halted* Functions/ Functions/ Halted Halted* Halted* Functions/ Functions/ Retained Halted* Halted* Functions/ Functions/ Retained Halted* Halted* Functions Retained Retained Note: * In active mode and sleep mode, if o W /2 is selected as the TCG internal clock, since the system clock and internal clock are not synchronized with each other, a synchronization circuit is used. This may result in a count cycle error of up to 1/o (s). In subactive mode and subsleep mode, if o W /2 is selected as the TCG internal clock, regardless of the subclock o/SUB (oW/2, oW /4, oW /8) TCG and the noise canceller circuit run on an internal clock of oW/2. If any other internal clock is chosen, TCG and the noise canceller circuit will not run, and the input capture function will not operate. 183 9.4.5 Application Notes Input Clock Switching and TCG Operation: Depending on when the input clock is switched, there will be cases in which TCG is incremented in the process. Table 9.11 shows the relation between internal clock switchover timing (selected in bits CKS1 and CKS0) and TCG operation. If an internal clock (derived from the system clock o or subclock o SUB ) is used, an increment pulse is generated when a falling edge of the internal clock is detected. For this reason, in a case like No. 3 in table 9.11, where the clock is switched at a time such that the clock signal goes from high level before switching to low level after switching, the switchover is seen as a falling edge to generate the count clock, causing TCG to be incremented. Table 9.11 Internal Clock Switching and TCG Operation Clock Levels Before and After Modifying Bits CKS1 and CKS0 Goes from low level to low level No. 1 TCG Operation Clock before switching Clock after switching Count clock TCG N CKS bits modified N +1 2 Goes from low level to high level Clock before switching Clock after switching Count clock TCG N N +1 N +2 CKS bits modified 184 Table 9.11 Internal Clock Switching and TCG Operation (cont) Clock Levels Before and After Modifying Bits CKS1 and CKS0 Goes from high level to low level No. 3 TCG Operation Clock before switching Clock after switching * Count clock TCG N N +1 CKS bits modified N +2 4 Goes from high level to high level Clock before switching Clock after switching Count clock TCG N N +1 N +2 CKS bits modified Note: * The switchover is seen as a falling edge of the clock pulse, and TCG is incremented. 185 Note on Rewriting Port Mode Registers: When a port mode register setting is modified to enable or disable the input capture function or input capture noise canceling function, note the following points. * Switching the function of the input capture pin When the function of the input capture pin is switched by modifying port mode register 1 (PMR1) bit 3 (the TMIG bit), an input capture edge may be recognized even though no valid signal edge has been input. This occurs under the conditions listed in table 9.12. Table 9.12 False Input Capture Edges Generating by Switching of Input Capture Pin Function Input Capture Edge Rising edge recognized Conditions TMIG pin level is high, and TMIG bit is changed from 0 to 1 TMIG pin level is high and NCS bit is changed from 0 to 1, then TMIG bit is changed from 0 to 1 before noise canceller circuit completes five samples Falling edge recognized TMIG pin level is high, and TMIG bit is changed from 1 to 0 TMIG pin level is low and NCS bit is changed from 0 to 1, then TMIG bit is changed from 0 to 1 before noise canceller circuit completes five samples TMIG pin level is high and NCS bit is changed from 0 to 1, then TMIG bit is changed from 1 to 0 before noise canceller circuit completes five samples Note: When pin P1 3 is not used for input capture, the input capture signal input to timer G is low. * Switching the input capture noise canceling function When modifying port mode register 2 (PMR2) bit 4 (the NCS bit) to enable or disable the input capture noise canceling function, first clear the TMIG bit to 0. Otherwise an input capture edge may be recognized even though no valid signal edge has been input. This occurs under the conditions listed in table 9.13. Table 9.13 False Input Capture Edges Generating by Switching of Noise Canceling Function Input Capture Edge Rising edge recognized Conditions TMIG bit is set to 1 and TMIG pin level changes from low to high, then NCS bit is changed from 1 to 0 before noise canceller circuit completes five samples TMIG bit is set to 1 and TMIG pin level changes from high to low, then NCS bit is changed from 1 to 0 before noise canceller circuit completes five samples Falling edge recognized 186 If switching of the pin function generates a false input capture edge matching the edge selected by the input capture interrupt edge select bit (IIEGS), the interrupt request flag will be set to 1, making it necessary to clear this flag to 0 before using the interrupt function. Figure 9.13 shows the procedure for modifying port mode register settings and clearing the interrupt request flag. The first step is to mask interrupts before modifying the port mode register. After modifying the port mode register setting, wait long enough for an input capture edge to be recognized (at least two system clocks when noise canceling is disabled; at least five sampling clocks when noise canceling is enabled), then clear the interrupt request flag to 0 (assuming it has been set to 1). An alternative procedure is to avoid having the interrupt request flag set when the pin function is switched, either by controlling the level of the input capture pin so that it does not satisfy the conditions in tables 9.12 and 9.13, or by setting the IIEGS bit of TMG to select the edge opposite to the falsely generated edge. Disable interrupts (or disable by clearing interrupt enable bit in interrupt enable register 2) Set I bit to 1 in CCR Modify port mode register Wait for TMIG to be recognized Clear interrupt request flag to 0 Modify port mode register setting, wait for input capture edge to be recognized (at least two system clocks when noise canceling is disabled; at least five sampling clocks when noise canceling is enabled), then clear interrupt request flag to 0 Clear I bit to 0 in CCR Enable interrupts Figure 9.13 Procedure for Modifying Port Mode Register and Clearing Interrupt Request Flag 187 9.4.6 Sample Timer G Application The absolute values of the high and low widths of the input capture signal can be measured by using timer G. The CCLR1 and CCLR0 bits of TMG should be set to 1. Figure 9.14 shows an example of this operation. Input capture signal H'FF Input capture register GF Input capture register GR H'00 TCG Counter cleared Figure 9.14 Sample Timer G Application 188 Section 10 Serial Communication Interface 10.1 Overview The H8/3627 Series is provided with a two-channel serial communication interface (SCI), SCI1 and SCI3. Table 10.1 summarizes the functions and features of the two SCI channels. Table 10.1 Serial Communication Interface Functions Channel SCI1 Functions Synchronous serial transfer * Choice of 8-bit or 16-bit data length * Continuous clock output Features * Choice of 8 internal clocks (o/1024 to o/2) or external clock * Open drain output possible * Interrupt requested at completion of transfer * * * * Built-in baud rate generator Receive error detection Break detection Interrupt requested at completion of transfer or error SCI3 Synchronous serial transfer * 8-bit data transfer * Send, receive, or simultaneous send/receive Asynchronous serial transfer * Multiprocessor communication function * Choice of 7-bit or 8-bit data length * Choice of 1-bit or 2-bit stop bit length * Odd or even parity 10.2 10.2.1 SCI1 Overview Serial communication interface 1 (SCI1) performs synchronous serial transfer of 8-bit or 16-bit data. Features: Features of SCI1 are given below. * Choice of 8-bit or 16-bit data length * Choice of eight internal clock sources (o/1024, o/256, o/64, o/32, o/16, o/8, o/4, o/2) or an external clock * Interrupt requested at completion of transfer 189 Block Diagram: Figure 10.1 shows a block diagram of SCI1. o PSS SCK1 SCR1 Transfer bit counter SI1 SDRU SDRL SO1 IRRS1 Legend: SCR1: SCSR1: SDRU: SDRL: IRRS1: PSS: Serial control register 1 Serial control/status register 1 Serial data register U Serial data register L SCI1 interrupt request flag Prescaler S Figure 10.1 SCI1 Block Diagram Pin Configuration: Table 10.2 shows the SCI1 pin configuration. Table 10.2 Pin Configuration Name SCI1 clock pin SCI1 data input pin SCI1 data output pin Abbrev. SCK 1 SI 1 SO1 I/O I/O Input Output Function SCI1 clock input or output SCI1 receive data input SCI1 transmit data output 190 Internal data bus Transmit/receive control circuit SCSR1 Register Configuration: Table 10.3 shows the SCI1 register configuration. Table 10.3 SCI1 Registers Name Serial control register 1 Serial control status register 1 Serial data register U Serial data register L Abbrev. SCR1 SCSR1 SDRU SDRL R/W R/W R/W R/W R/W Initial Value H'00 H'9C Undefined Undefined Address H'FFA0 H'FFA1 H'FFA2 H'FFA3 10.2.2 Register Descriptions Serial Control Register 1 (SCR1) Bit 7 SNC1 Initial value Read/Write 0 R/W 6 SNC0 0 R/W 5 -- 0 R/W 4 -- 0 R/W 3 CKS3 0 R/W 2 CKS2 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W SCR1 is an 8-bit read/write register for selecting the operation mode, the transfer clock source, and the prescaler division ratio. Upon reset, SCR1 is initialized to H'00. Writing to this register stops a transfer in progress. Bits 7 and 6--Operation Mode Select 1, 0 (SNC1, SNC0): Bits 7 and 6 select the operation mode. Bit 7: SNC1 0 Bit 6: SNC0 0 1 1 0 1 Description 8-bit synchronous transfer mode 16-bit synchronous transfer mode Continuous clock output mode* 1 Reserved * 2 (initial value) Notes: 1. Pins SI 1 and SO1 should be used as general input or output ports. 2. Don't set bits SNC1 and SNC0 to 11. Bits 5 and 4--Reserved Bits: Bits 5 and 4 are reserved: they should always be cleared to 0. 191 Bit 3--Clock Source Select 3 (CKS3): Bit 3 selects the clock source and sets pin SCK1 as an input or output pin. Bit 3: CKS3 0 1 Description Clock source is prescaler S, and pin SCK 1 is output pin Clock source is external clock, and pin SCK1 is input pin (initial value) Bits 2 to 0--Clock Select 2 to 0 (CKS2 to CKS 0): When CKS3 = 0, bits 2 to 0 select the prescaler division ratio and the serial clock cycle. Serial Clock Cycle Bit 2: CKS2 0 Bit 1: CKS1 0 Bit 0: CKS0 0 1 1 0 1 1 0 0 1 1 0 1 Prescaler Division o/1024 (initial value) o/256 o/64 o/32 o/16 o/8 o/4 o/2 o = 5 MHz 204.8 s 51.2 s 12.8 s 6.4 s 3.2 s 1.6 s 0.8 s -- o = 2.5 MHz 409.6 s 102.4 s 25.6 s 12.8 s 6.4 s 3.2 s 1.6 s 0.8 s Serial Control/Status Register 1 (SCSR1) Bit 7 -- Initial value Read/Write 1 -- 6 SOL 0 R/W 5 ORER 0 R/(W)* 4 -- 1 -- 3 -- 1 -- 2 -- 1 -- 1 -- 0 R 0 STF 0 R/W Note: * Only a write of 0 for flag clearing is possible. SCSR1 is an 8-bit read/write register indicating operation status and error status. Upon reset, SCSR1 is initialized to H'9C. Bit 7--Reserved Bit: Bit 7 is reserved; it is always read as 1, and cannot be modified. 192 Bit 6--Extended Data Bit (SOL): Bit 6 sets the SO1 output level. When read, SOL returns the output level at the SO1 pin. After completion of a transmission, SO1 continues to output the value of the last bit of transmitted data. The SO1 output can be changed by writing to SOL before or after a transmission. The SOL bit setting remains valid only until the start of the next transmission. To control the level of the SO1 pin after transmission ends, it is necessary to write to the SOL bit at the end of each transmission. Do not write to this register while transmission is in progress, because that may cause a malfunction. Bit 6: SOL 0 Description Read Write 1 Read Write SO1 pin output level is low SO1 pin output level changes to low SO1 pin output level is high SO1 pin output level changes to high (initial value) Bit 5--Overrun Error Flag (ORER): When an external clock is used, bit 5 indicates the occurrence of an overrun error. If a clock pulse is input after transfer completion, this bit is set to 1 indicating an overrun. If noise occurs during a transfer, causing an extraneous pulse to be superimposed on the normal serial clock, incorrect data may be transferred. Bit 5: ORER 0 1 Description [Clearing conditions] After reading ORER = 1, cleared by writing 0 to ORER (initial value) [Setting conditions] Set if a clock pulse is input after transfer is complete, when an external clock is used Bits 4 to 2--Reserved Bits: Bits 4 to 2 are reserved; they are always read as 1, and cannot be modified. Bit 1--Reserved Bit: Bit 1 is reserved; and cannot be modified. This bit will be read as 0 after a reset, but its value is undefined at other times. Bit 0--Start Flag (STF): Bit 0 controls the start of a transfer. Setting this bit to 1 causes SCI1 to start transferring data. During the transfer or while waiting for start bit, this bit remains set to 1. It is cleared to 0 upon completion of the transfer. It can therefore be used as a busy flag. 193 Bit 0: STF 0 Description Read Write Indicates that transfer is stopped Invalid Indicates transfer in progress Starts a transfer operation (initial value) 1 Read Write Serial Data Register U (SDRU) Bit 7 SDRU7 Initial value Read/Write 6 SDRU6 5 SDRU5 4 SDRU4 3 SDRU3 2 SDRU2 1 SDRU1 0 SDRU0 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W R/W R/W R/W R/W SDRU is an 8-bit read/write register. It is used as the data register for the upper 8 bits in 16-bit transfer (SDRL is used for the lower 8 bits). Data written to SDRU is output to SDRL starting from the least significant bit (LSB). This data is then replaced by LSB-first data input at pin SI1, which is shifted in the direction from the most significant bit (MSB) toward the LSB. SDRU must be written or read only after data transmission or reception is complete. If this register is written or read while a data transfer is in progress, the data contents are not guaranteed. The SDRU value upon reset is not fixed. Serial Data Register L (SDRL) Bit 7 SDRL7 Initial value Read/Write 6 SDRL6 5 SDRL5 4 SDRL4 3 SDRL3 2 SDRL2 1 SDRL1 0 SDRL0 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R/W R/W R/W R/W R/W R/W R/W R/W SDRL is an 8-bit read/write register. It is used as the data register in 8-bit transfer, and as the data register for the lower 8 bits in 16-bit transfer (SDRU is used for the upper 8 bits). In 8-bit transfer, data written to SDRL is output from pin SO1 starting from the least significant bit (LSB). This data is than replaced by LSB-first data input at pin SI1, which is shifted in the direction from the most significant bit (MSB) toward the LSB. In 16-bit transfer, operation is the same as for 8-bit transfer, except that input data is fed in via SDRU. 194 SDRL must be written or read only after data transmission or reception is complete. If this register is read or written while a data transfer is in progress, the data contents are not guaranteed. The SDRL value upon reset is not fixed. 10.2.3 Operation Data can be sent and received in an 8-bit or 16-bit format, synchronized to an internal or external clock. Overrun errors can be detected when an external clock is used. (1) Clock The serial clock can be selected from a choice of eight internal clocks and an external clock. When an internal clock source is selected, pin SCK1 becomes the clock output pin. When continuous clock output mode is selected (SCR1 bits SNC1 and SNC0 are set to 10), the clock signal (o/1024 to o/2) selected in bits CKS2 to CKS0 is output continuously from pin SCK1. When an external clock is used, pin SCK1 is the clock input pin. (2) Data transfer format Figure 10.2 shows the data transfer format. Data is sent and received starting from the least significant bit, in LSB-first format. Transmit data is output from one falling edge of the serial clock until the next falling edge. Receive data is latched at the rising edge of the serial clock. SCK 1 SO1 /SI 1 Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Figure 10.2 Transfer Format (3) Data transfer Operations Transmitting: A transmit operation is carried out as follows. 1. Set bits SO1 and SCK1 in PMR2 to 1, selecting the SO1 and SCK1 pin functions. If necessary, set bit POF1 in PMR2 for NMOS open drain output at pin SO1. 2. Clear bit SNC1 in SCR1 to 0, and set bit SNC0 to 1 or 0, designating 8- or 16-bit synchronous transfer mode. Select the serial clock in bits CKS3 to CKS0. Writing data to SCR1 initializes the internal state of SCI1. 3. Write transmit data in SDRL and SDRU, as follows. 8-bit transfer mode: SDRL 16-bit transfer mode: Upper byte in SDRU, lower byte in SDRL 4. Set the SCSR1 start flag (STF) to 1. SCI1 starts operating and outputs transmit data at pin SO1. 195 5. After data transmission is complete, bit IRRS1 in interrupt request register 1 (IRR1) is set to 1. When an internal clock is used, a serial clock is output from pin SCK1 in synchronization with the transmit data. After data transmission is complete, the serial clock is not output until the next time the start flag is set to 1. During this time, pin SO1 continues to output the value of the last bit transmitted. When an external clock is used, data is transmitted in synchronization with the serial clock input at pin SCK1. After data transmission is complete, an overrun occurs if the serial clock continues to be input; no data is transmitted and the SCSR1 overrun error flag (bit ORER) is set to 1. While transmission is stopped, the output value of pin SO1 can be changed by rewriting bit SOL in SCSR1. Receiving: A receive operation is carried out as follows. 1. Set bits SI1 and SCK1 in PMR2 to 1, selecting the SI1 and SCK1 pin functions. 2. Clear bit SNC1 in SCR1 to 0, and set bit SNC0 to 1 or 0, designating 8- or 16-bit synchronous transfer mode. Select the serial clock in bits CKS3 to CKS0. Writing data to SCR1 initializes the internal state of SCI1. 3. Set the SCSR1 start flag (STF) to 1. SCI1 starts operating and receives data at pin SI 1. 4. After data reception is complete, bit IRRS1 in interrupt request register 1 (IRR1) is set to 1. 5. Read the received data from SDRL and SDRU, as follows. 8-bit transfer mode: SDRL 16-bit transfer mode: Upper byte in SDRU, lower byte in SDRL 6. After data reception is complete, an overrun occurs if the serial clock continues to be input; no data is received and the SCSR1 overrun error flag (bit ORER) is set to 1. Simultaneous Transmit/Receive: A simultaneous transmit/receive operation is carried out as follows. 1. Set bits SO1, SI1, and SCK1 in PMR2 to 1, selecting the SO1, SI1, and SCK1 pin functions. If necessary, set bit POF1 in PMR2 for NMOS open drain output at pin SO 1. 2. Clear bit SNC1 in SCR1 to 0, and set bit SNC0 to 1 or 0, designating 8- or 16-bit synchronous transfer mode. Select the serial clock in bits CKS3 to CKS0. Writing data to SCR1 initializes the internal state of SCI1. 3. Write transmit data in SDRL and SDRU, as follows. 8-bit transfer mode: SDRL 16-bit transfer mode: Upper byte in SDRU, lower byte in SDRL 4. Set the SCSR1 start flag (STF) to 1. SCI1 starts operating. Transmit data is output at pin SO 1. Receive data is input at pin SI1. 5. After data transmission and reception are complete, bit IRRS1 in IRR1 is set to 1. 196 6. Read the received data from SDRL and SDRU, as follows. 8-bit transfer mode: SDRL 16-bit transfer mode: Upper byte in SDRU, lower byte in SDRL When an internal clock is used, a serial clock is output from pin SCK1 in synchronization with the transmit data. After data transmission is complete, the serial clock is not output until the next time the start flag is set to 1. During this time, pin SO1 continues to output the value of the last bit transmitted. When an external clock is used, data is transmitted and received in synchronization with the serial clock input at pin SCK 1. After data transmission and reception are complete, an overrun occurs if the serial clock continues to be input; no data is transmitted or received and the SCSR1 overrun error flag (bit ORER) is set to 1. While transmission is stopped, the output value of pin SO1 can be changed by rewriting bit SOL in SCSR1. 10.2.4 Interrupt Sources SCI1 can generate an interrupt at the end of a data transfer. When an SCI1 transfer is complete, bit IRRS1 in interrupt request register 1 (IRR1) is set to 1. SCI1 interrupt requests can be enabled or disabled by bit IENS1 of interrupt enable register 1 (IENR1). For further details, see 3.3, Interrupts. 197 10.3 10.3.1 SCI3 Overview Serial communication interface 3 (SCI3) has both synchronous and asynchronous serial data communication capabilities. It also has a multiprocessor communication function for serial data communication among two or more processors. Features: SCI3 features are listed below. * Selection of asynchronous or synchronous mode Asynchronous mode Serial data communication is performed using the asynchronous method, in which synchronization is achieved character by character. SCI3 can communicate with a UART (universal asynchronous receiver/transmitter), ACIA (asynchronous communication interface adapter), or other chip that employs standard asynchronous serial communication. It can also communicate with two or more other processors using the multiprocessor communication function. There are twelve selectable serial data communication formats. * Data length: seven or eight bits * Stop bit length: one or two bits * Parity: even, odd, or none * Multiprocessor bit: one or none * Receive error detection: parity, overrun, and framing errors * Break detection: by reading the RXD level directly when a framing error occurs Synchronous mode Serial data communication is synchronized with a clock signal. SCI3 can communicate with other chips having a clocked synchronous communication function. * Data length: eight bits * Receive error detection: overrun errors * Full duplex communication The transmitting and receiving sections are independent, so SCI3 can transmit and receive simultaneously. Both sections use double buffering, so continuous data transfer is possible in both the transmit and receive directions. * Built-in baud rate generator with selectable bit rates. * Internal or external clock may be selected as the transfer clock source. * There are six interrupt sources: transmit end, transmit data register empty, receive data register full, overrun error, framing error, and parity error. 198 Block Diagram: Figure 10.3 shows a block diagram of SCI3. External clock Baud rate generator BRC Clock SMR Transmit/receive control SCR3 SSR Internal data bus Interrupt requests (TEI, TXI, RXI, ERI) SCK 3 Internal clock (o/64, o/16, o/4, o) BRR TXD TSR TDR RXD RSR RDR Legend: RSR: Receive shift register RDR: Receive data register TSR: Transmit shift register TDR: Transmit data register SMR: Serial mode register SCR3: Serial control register 3 SSR: Serial status register BRR: Bit rate register BRC: Bit rate counter Figure 10.3 SCI3 Block Diagram 199 Pin Configuration: Table 10.4 shows the SCI3 pin configuration. Table 10.4 Pin Configuration Name SCI3 clock SCI3 receive data input SCI3 transmit data output Abbrev. SCK 3 RXD TXD I/O I/O Input Output Function SCI3 clock input/output SCI3 receive data input SCI3 transmit data output Register Configuration: Table 10.5 shows the SCI3 internal register configuration. Table 10.5 SCI3 Registers Name Serial mode register Bit rate register Serial control register 3 Transmit data register Serial status register Receive data register Transmit shift register Receive shift register Bit rate counter Abbrev. SMR BRR SCR3 TDR SSR RDR TSR RSR BRC R/W R/W R/W R/W R/W R/W R Not possible Not possible Not possible Initial Value H'00 H'FF H'00 H'FF H'84 H'00 -- -- -- Address H'FFA8 H'FFA9 H'FFAA H'FFAB H'FFAC H'FFAD -- -- -- 10.3.2 Register Descriptions Receive Shift Register (RSR) Bit Read/Write 7 -- 6 -- 5 -- 4 -- 3 -- 2 -- 1 -- 0 -- The receive shift register (RSR) is for receiving serial data. Serial data is input in LSB-first order into RSR from pin RXD, converting it to parallel data. After each byte of data has been received, the byte is automatically transferred to the receive data register (RDR). RSR cannot be read or written directly by the CPU. 200 Receive Data Register (RDR) Bit 7 RDR7 Initial value Read/Write 0 R 6 RDR6 0 R 5 RDR5 0 R 4 RDR4 0 R 3 RDR3 0 R 2 RDR2 0 R 1 RDR1 0 R 0 RDR0 0 R The receive data register (RDR) is an 8-bit register for storing received serial data. Each time a byte of data is received, the received data is transferred from the receive shift register (RSR) to RDR, completing a receive operation. Thereafter RSR again becomes ready to receive new data. RSR and RDR form a double buffer mechanism that allows data to be received continuously. RDR is exclusively for receiving data and cannot be written by the CPU. RDR is initialized to H'00 upon reset or in standby mode, watch mode, subactive mode, or subsleep mode. Transmit Shift Register (TSR) Bit 7 6 5 4 3 2 1 0 Read/Write -- -- -- -- -- -- -- -- The transmit shift register (TSR) is for transmitting serial data. Transmit data is first transferred from the transmit data register (TDR) to TSR, then is transmitted from pin TXD, starting from the LSB (bit 0). After one byte of data has been sent, the next byte is automatically transferred from TDR to TSR, and the next transmission begins. If no data has been written to TDR (1 is set in TDRE), there is no data transfer from TDR to TSR. TSR cannot be read or written directly by the CPU. 201 Transmit Data Register (TDR) Bit 7 TDR7 Initial value Read/Write 1 R/W 6 TDR6 1 R/W 5 TDR5 1 R/W 4 TDR4 1 R/W 3 TDR3 1 R/W 2 TDR2 1 R/W 1 TDR1 1 R/W 0 TDR0 1 R/W The transmit data register (TDR) is an 8-bit register for holding transmit data. When SCI3 detects that the transmit shift register (TSR) is empty, it shifts transmit data written in TDR to TSR and starts serial data transmission. While TSR is transmitting serial data, the next byte to be transmitted can be written to TDR, realizing continuous transmission. TDR can be read or written by the CPU at all times. TDR is initialized to H'FF upon reset or in standby mode, watch mode, subactive mode, or subsleep mode. Serial Mode Register (SMR) Bit 7 COM Initial value Read/Write 0 R/W 6 CHR 0 R/W 5 PE 0 R/W 4 PM 0 R/W 3 STOP 0 R/W 2 MP 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W The serial mode register (SMR) is an 8-bit register for setting the serial data communication format and for selecting the clock source of the baud rate generator. SMR can be read and written by the CPU at any time. SMR is initialized to H'00 upon reset or in standby mode, watch mode, subactive mode, or subsleep mode. Bit 7--Communication Mode (COM): Bit 7 selects asynchronous mode or synchronous mode as the serial data communication mode. Bit 7: COM 0 1 Description Asynchronous mode Synchronous mode (initial value) 202 Bit 6--Character Length (CHR): Bit 6 selects either 7 bits or 8 bits as the data length in asynchronous mode. In synchronous mode the data length is always 8 bits regardless of the setting here. Bit 6: CHR 0 1 Description 8-bit data 7-bit data* (initial value) Note: * When 7-bit data is selected as the character length in asynchronous mode, the MSB (bit 7) in the transmit data register is not transmitted. Bit 5--Parity Enable (PE): In asynchronous mode, bit 5 selects whether or not a parity bit is to be added to transmitted data and checked in received data. In synchronous mode there is no adding or checking of parity regardless of the setting here. Bit 5: PE 0 1 Description Parity bit adding and checking disabled Parity bit adding and checking enabled* (initial value) Note: * When PE is set to 1, then either odd or even parity is added to transmit data, depending on the setting of the parity mode bit (PM). When data is received, it is checked for odd or even parity as designated in bit PM. Bit 4--Parity Mode (PM): In asynchronous mode, bit 4 selects whether odd or even parity is to be added to transmitted data and checked in received data. The setting here is valid only if parity adding/checking is enabled in bit PE. In synchronous mode, or if parity adding/checking is disabled in asynchronous mode, bit PM is ignored. Bit 4: PM 0 1 Description Even parity* 1 Odd parity * 2 (initial value) Notes: 1. When even parity is designated, a parity bit is added to the transmitted data so that the sum of 1s in the resulting data is an even number. When data is received, the sum of 1s in the data plus parity bit is checked to see if the result is an even number. 2. When odd parity is designated, a parity bit is added to the transmitted data so that the sum of 1s in the resulting data is an odd number. When data is received, the sum of 1s in the data plus parity bit is checked to see if the result is an odd number. 203 Bit 3--Stop Bit Length (STOP): Bit 3 selects 1 bit or 2 bits as the stop bit length in asynchronous mode. This setting is valid only in asynchronous mode. In synchronous mode a stop bit is not added, so this bit is ignored. Bit 3: STOP 0 1 Description 1 stop bit * 1 2 stop bits* 2 (initial value) Notes: 1. When data is transmitted, one "1" bit is added at the end of each transmitted character as the stop bit. 2. When data is transmitted, two "1" bits are added at the end of each transmitted character as the stop bits. When data is received, only the first stop bit is checked regardless of the stop bit length. If the second stop bit value is 1 it is treated as a stop bit; if it is 0, it is treated as the start bit of the next character. Bit 2--Multiprocessor Mode (MP): Bit 2 enables or disables the multiprocessor communication function. When the multiprocessor communication function is enabled, the parity enable (PE) and parity mode (PM) settings are ignored. The MP bit is valid only in asynchronous mode; it should be cleared to 0 in synchronous mode. See 10.3.6, for details on the multiprocessor communication function. Bit 2: MP 0 1 Description Multiprocessor communication function disabled Multiprocessor communication function enabled (initial value) Bits 1 and 0--Clock Select 1, 0 (CKS1, CKS0): Bits 1 and 0 select the clock source for the builtin baud rate generator. A choice of o/64, o/16, o/4, or o is made in these bits. See 8, Bit rate register, below for information on the clock source and bit rate register settings, and their relation to the baud rate. Bit 1: CKS1 0 Bit 0: CKS0 0 1 1 0 1 Description o clock o/4 clock o/16 clock o/64 clock (initial value) 204 Serial Control Register 3 (SCR3) Bit 7 TIE Initial value Read/Write 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W 3 MPIE 0 R/W 2 TEIE 0 R/W 1 CKE1 0 R/W 0 CKE0 0 R/W Serial control register 3 (SCR3) is an 8-bit register that controls SCI3 transmit and receive operations, enables or disables serial clock output in asynchronous mode, enables or disables interrupts, and selects the serial clock source. SCR3 can be read and written by the CPU at any time. SCR3 is initialized to H'00 upon reset or in standby mode, watch mode, subactive mode, or subsleep mode. Bit 7--Transmit Interrupt Enable (TIE): Bit 7 enables or disables the transmit data empty interrupt request (TXI) when data is transferred from TDR to TSR and the transmit data register empty bit (TDRE) in the serial status register (SSR) is set to 1. The TXI interrupt can be cleared by clearing bit TDRE to 0, or by clearing bit TIE to 0. Bit 7: TIE 0 1 Description Transmit data empty interrupt request (TXI) disabled Transmit data empty interrupt request (TXI) enabled (initial value) Bit 6--Receive Interrupt Enable (RIE): Bit 6 enables or disables the receive error interrupt request (ERI), and the receive data full interrupt request (RXI) when data is transferred from RSR to RDR and the receive data register full bit (RDRF) in the serial status register (SSR) is set to 1. Receive errors include overrun errors, framing errors, and parity errors. RXI and ERI interrupts can be cleared by clearing SSR flag RDRF, or flags FER, PER, and OER to 0, or by clearing bit RIE to 0. Bit 6: RIE 0 1 Description Receive data full interrupt request (RXI) and receive error interrupt request (ERI) disabled (initial value) Receive data full interrupt request (RXI) and receive error interrupt request (ERI) enabled 205 Bit 5--Transmit Enable (TE): Bit 5 enables or disables the start of a transmit operation. Bit 5: TE 0 1 Description Transmit operation disabled* 1 (TXD is the transmit data pin) Transmit operation enabled * (TXD is the transmit data pin) 2 (initial value) Notes: 1. The transmit data register empty bit (TDRE) in the serial status register (SSR) is fixed at 1. Transmit operations are disabled, but the TXD pin functions as the transmit data pin. To use the TXD pin as an I/O pin, clear bit TXD in PMR6 to 0. 2. In this state, writing transmit data in TDR clears bit TDRE in SSR to 0 and starts serial data transmission. Before setting TE to 1 it is necessary to set the transmit format in SMR. Bit 4--Receive Enable (RE): Bit 4 enables or disables the start of a receive operation. Bit 4: RE 0 1 Description Receive operation disabled * 1 (RXD is a general I/O port) Receive operation enabled* (RXD is the receive data pin) 2 (initial value) Notes: 1. When RE is cleared to 0, this has no effect on the SSR flags RDRF, FER, PER, and OER, which retain their states. 2. Serial data receiving begins when, in this state, a start bit is detected in asynchronous mode, or serial clock input is detected in synchronous mode. Before setting RE to 1 it is necessary to set the receive format in SMR. Bit 3--Multiprocessor Interrupt Enable (MPIE): Bit 3 enables or disables multiprocessor interrupt requests. This setting is valid only in asynchronous mode, and only when the multiprocessor mode bit (MP) in the serial mode register (SMR) is set to 1. It applies only to data receiving. This bit is ignored when COM is set to 1 or when bit MP is cleared to 0. Bit 3: MPIE 0 Description Multiprocessor interrupt request disabled (ordinary receive operation) (initial value) [Clearing condition] Multiprocessor bit receives a data value of 1 1 Multiprocessor interrupt request enabled* Note: * SCI3 does not transfer receive data from RSR to RDR, does not detect receive errors, and does not set status flags RDRF, FER, and OER in SSR. Until a multiprocessor bit value of 1 is received, the receive data full interrupt (RXI) and receive error interrupt (ERI) are disabled and serial status register (SSR) flags RDRF, FER, and OER are not set. When the multiprocessor bit receives a 1, the MPBR bit of SSR is set to 1, MPIE is automatically cleared to 0, RXI and ERI interrupts are enabled (provided bits TIE and RIE in SCR3 are set to 1), and setting of the RDRF, FER, and OER flags is enabled. 206 Bit 2--Transmit End Interrupt Enable (TEIE): Bit 2 enables or disables the transmit end interrupt (TEI) requested if there is no valid transmit data in TDR when the MSB is transmitted. Bit 2: TEIE 0 1 Description Transmit end interrupt (TEI) disabled Transmit end interrupt (TEI) enabled* (initial value) Note: * A TEI interrupt can be cleared by clearing the SSR bit TDRE to 0 and clearing the transmit end bit (TEND) to 0, or by clearing bit TEIE to 0. Bits 1 and 0--Clock Enable 1, 0 (CKE1, CKE0): Bits 1 and 0 select the clock source and enable or disable clock output at pin SCK3. The combination of bits CKE1 and CKE0 determines whether pin SCK3 is a general I/O port, a clock output pin, or a clock input pin. Note that the CKE0 setting is valid only when operation is in asynchronous mode using an internal clock (CKE1 = 0). This bit is invalid in synchronous mode or when using an external clock (CKE1 = 1). In synchronous mode and in external clock mode, clear CKE0 to 0. After setting bits CKE1 and CKE0, the operation mode must first be set in the serial mode register (SMR). See table 10.10 in 10.3.3, Operation, for details on clock source selection. Description Bit 1: CKE1 0 Bit 0: CKE0 0 Communication Mode Asynchronous Synchronous 1 Asynchronous Synchronous 1 0 Asynchronous Synchronous 1 Asynchronous Synchronous Clock Source Internal clock Internal clock Internal clock Reserved External clock External clock Reserved Reserved SCK3 Pin Function I/O port* 1 Serial clock output * 1 Clock output* 2 Reserved Clock input * 3 Serial clock input Reserved Reserved Notes: 1. Initial value 2. A clock is output with the same frequency as the bit rate. 3. Input a clock with a frequency 16 times the bit rate. 207 Serial Status Register (SSR) Bit 7 TDRE Initial value Read/Write 1 R/(W)* 6 RDRF 0 R/(W)* 5 OER 0 R/(W)* 4 FER 0 R/(W)* 3 PER 0 R/(W)* 2 TEND 1 R 1 MPBR 0 R 0 MPBT 0 R/W Note: * Only a write of 0 for flag clearing is possible. The serial status register (SSR) is an 8-bit register containing status flags for indicating SCI3 states, and containing the multiprocessor bits. SSR can be read and written by the CPU at any time, but the CPU cannot write a 1 to the status flags TDRE, RDRF, OER, PER, and FER. To clear these flags to 0 it is first necessary to read a 1. Bit 2 (TEND) and bit 1 (MPBR) are read-only bits and cannot be modified. SSR is initialized to H'84 upon reset or in standby mode, watch mode, subactive mode, or subsleep mode. Bit 7--Transmit Data Register Empty (TDRE): Bit 7 is a status flag indicating that data has been transferred from TDR to TSR. Bit 7: TDRE 0 Description Indicates that transmit data written to TDR has not been transferred to TSR [Clearing conditions] * * 1 After reading TDRE = 1, cleared by writing 0 to TDRE. When data is written to TDR by an instruction. Indicates that no transmit data has been written to TDR, or the transmit data written to TDR has been transferred to TSR (initial value) [Setting conditions] * * When bit TE in SCR3 is cleared to 0. When data is transferred from TDR to TSR. 208 Bit 6--Receive Data Register Full (RDRF): Bit 6 is a status flag indicating whether there is receive data in RDR. Bit 6: RDRF 0 Description Indicates there is no receive data in RDR [Clearing conditions] * * 1 After reading RDRF = 1, cleared by writing 0 to RDRF. When data is read from RDR by an instruction. (initial value) Indicates that there is receive data in RDR [Setting condition] When receiving ends normally, with receive data transferred from RSR to RDR Note: If a receive error is detected during data receiving, or if bit RE in serial control register 3 (SCR3) is cleared to 0, RDR and RDRF are unaffected and keep their previous states. An overrun error (OER) occurs if receiving of data is completed while bit RDRF remains set to 1. If this happens, receive data will be lost. Bit 5--Overrun Error (OER): Bit 5 is a status flag indicating that an overrun error has occurred during data receiving. Bit 5: OER 0 Description Indicates that data receiving is in progress or has been completed* 1 (initial value) [Clearing condition] After reading OER = 1, cleared by writing 0 to OER 1 Indicates that an overrun error occurred in data receiving* 2 [Setting condition] When data receiving is completed while RDRF is set to 1 Notes: 1. When bit RE in serial control register 3 (SCR3) is cleared to 0, OER is unaffected and keeps its previous state. 2. RDR keeps the data received prior to the overrun; data received after that is lost. While OER is set to 1, data receiving cannot be continued. In synchronous mode, data transmitting cannot be continued either. 209 Bit 4: Framing Error (FER): Bit 4 is a status flag indicating that a framing error has occurred during asynchronous receiving. Bit 4: FER 0 Description Indicates that data receiving is in progress or has been completed* 1 (initial value) [Clearing condition] After reading FER = 1, cleared by writing 0 to FER 1 Indicates that a framing error occurred in data receiving [Setting condition] The stop bit at the end of receive data is checked and found to be 0 * 2 Notes: 1. When bit RE in serial control register 3 (SCR3) is cleared to 0, FER is unaffected and keeps its previous state. 2. When two stop bits are used only the first stop bit is checked, not the second. When a framing error occurs, receive data is transferred to RDR but RDRF is not set. While FER is set to 1, data receiving cannot be continued. In synchronous mode, data transmission and reception cannot be performed if FER is set to 1. Bit 3--Parity Error (PER): Bit 3 is a status flag indicating that a parity error has occurred during asynchronous receiving. Bit 3: PER 0 Description Indicates that data receiving is in progress or has been completed* 1 (initial value) [Clearing condition] After reading PER = 1, cleared by writing 0 to PER 1 Indicates that a parity error occurred in data receiving * 2 [Setting condition] When the sum of 1s in received data plus the parity bit does not match the parity mode bit (PM) setting in the serial mode register (SMR) Notes: 1. When bit RE in serial control register 3 (SCR3) is cleared to 0, PER is unaffected and keeps its previous state. 2. When a parity error occurs, receive data is transferred to RDR but RDRF is not set. While PER is set to 1, data receiving cannot be continued. While PER is set to 1 in synchronous mode, data transmission and reception cannot be performed. 210 Bit 2--Transmit End (TEND): Bit 2 is a status flag indicating that TDRE was set to 1 when the last bit of a transmitted character was sent. TEND is a read-only bit and cannot be modified. Bit 2: TEND 0 Description Indicates that transmission is in progress [Clearing conditions] * * 1 After reading TDRE = 1, cleared by writing 0 to TDRE. When data is written to TDR by an instruction. (initial value) Indicates that a transmission has ended [Setting conditions] * * When bit TE in SCR3 is cleared to 0. If TDRE is set to 1 when the last bit of a transmitted character is sent. Bit 1--Multiprocessor Bit Receive (MPBR): Bit 1 holds the multiprocessor bit in data received in asynchronous mode using a multiprocessor format. MPBR is a read-only bit and cannot be modified. Bit 1: MPBR 0 1 Description Indicates reception of data in which the multiprocessor bit is 0* (initial value) Indicates reception of data in which the multiprocessor bit is 1 Note: * If bit RE in SCR3 is cleared to 0 while a multiprocessor format is in use, MPBR retains its previous state. Bit 0--Multiprocessor Bit Transmit (MPBT): Bit 0 holds the multiprocessor bit to be added to transmitted data when a multiprocessor format is used in asynchronous mode. Bit MPBT is ignored when synchronous mode is chosen, when the multiprocessor communication function is disabled, or when data transmission is disabled. Bit 0: MPBT 0 1 Description The multiprocessor bit in transmit data is 0 The multiprocessor bit in transmit data is 1 (initial value) 211 Bit Rate Register (BRR) Bit 7 BRR7 Initial value Read/Write 1 R/W 6 BRR6 1 R/W 5 BRR5 1 R/W 4 BRR4 1 R/W 3 BRR3 1 R/W 2 BRR2 1 R/W 1 BRR1 1 R/W 0 BRR0 1 R/W The bit rate register (BRR) is an 8-bit register which, together with the baud rate generator clock selected by bits CKS1 and CKS0 in the serial mode register (SMR), sets the transmit/receive bit rate. BRR can be read or written by the CPU at any time. BRR is initialized to H'FF upon reset or in standby mode, watch mode, subactive mode, or subsleep mode. Table 10.6 gives examples of how BRR is set in asynchronous mode. The values in table 10.6 are for active (high-speed) mode. 212 Table 10.6 BRR Settings and Bit Rates in Asynchronous Mode OSC (MHz) 2 2.4576 Error (%) +0.03 +0.16 +0.16 +0.16 +0.16 +0.16 -- -- -- 0 -- n 1 0 0 0 0 0 0 0 0 -- 0 N 86 255 127 63 31 15 7 3 1 -- 0 Error (%) +0.31 0 0 0 0 0 0 0 0 -- 0 n 1 1 0 0 0 0 0 -- -- 0 -- N 141 103 207 103 51 25 12 -- -- 1 -- 4 Error (%) +0.03 +0.16 +0.16 +0.16 +0.16 +0.16 +0.16 -- -- 0 -- n 1 1 0 0 0 0 0 0 -- -- -- 4.194304 N 148 108 217 108 54 26 13 6 -- -- -- Error (%) -0.04 +0.21 +0.21 +0.21 -0.70 +1.14 -2.48 -2.48 -- -- -- Bit Rate (bits/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 1 0 0 0 0 0 -- -- -- 0 -- N 70 207 103 51 25 12 -- -- -- 0 -- Table 10.6 BRR Settings and Bit Rates in Asynchronous Mode (cont) OSC (MHz) 4.9152 Bit Rate (bits/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 1 1 0 0 0 0 0 0 0 -- 0 N 174 127 255 127 63 31 15 7 3 -- 1 Error (%) -0.26 0 0 0 0 0 0 0 0 -- 0 n 1 1 1 0 0 0 0 0 0 0 -- N 212 155 77 155 77 38 19 9 4 2 -- 6 Error (%) +0.03 +0.16 +0.16 +0.16 +0.16 +0.16 -2.34 -2.34 -2.34 0 -- n 2 1 1 0 0 0 0 0 0 -- 0 7.3728 N 64 191 95 191 95 47 23 11 5 -- 2 Error (%) +0.70 0 0 0 0 0 0 0 0 -- 0 n 2 1 1 0 0 0 0 0 -- 0 -- N 70 207 103 207 103 51 25 12 -- 3 -- 8 Error (%) +0.03 +0.16 +0.16 +0.16 +0.16 +0.16 +0.16 +0.16 -- 0 -- 213 Table 10.6 BRR Settings and Bit Rates in Asynchronous Mode (cont) OSC (MHz) 9.8304 Bit Rate (bits/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 2 1 1 0 0 0 0 0 0 0 0 N 86 255 127 255 127 63 31 15 7 4 3 Error (%) +0.31 0 0 0 0 0 0 0 0 -1.70 0 n 2 2 1 1 0 0 0 0 0 0 0 N 88 64 129 64 129 64 32 15 7 4 3 10 Error (%) -0.25 +0.16 +0.16 +0.16 +0.16 +0.16 -1.36 +1.73 +1.73 0 +1.73 Notes: 1. Settings should be made so that error is within 1%. 2. BRR setting values are derived by the following equation. N= OSC x 106 - 1 64 x 22n x B Bit rate (bits/s) BRR baud rate generator setting (0 N 255) Value of oOSC (MHz) Baud rate generator input clock number (n = 0, 1, 2, 3) The meaning of n is shown in table 10.7. B: N: OSC: n: Table 10.7 Relation between n and Clock SMR Setting n 0 1 2 3 Clock o o/4 o16 o/64 CKS1 0 0 1 1 CKS0 0 1 0 1 214 3. The error values in table 10.6 were derived by performing the following calculation and rounding off to two decimal places. Error (%) = B-R R x 100 B: Bit rate found from n, N, and OSC R: Bit rate listed in left column of table 10.6 Table 10.8 shows the maximum bit rate for selected frequencies in asynchronous mode. Values in table 10.8 are for active (high-speed) mode. Table 10.8 Maximum Bit Rate at Selected Frequencies (Asynchronous Mode) Setting OSC (MHz) 2 2.4576 4 4.194304 4.9152 6 7.3728 8 9.8304 10 Maximum Bit Rate (bits/s) 31250 38400 62500 65536 76800 93750 115200 125000 153600 156250 n 0 0 0 0 0 0 0 0 0 0 N 0 0 0 0 0 0 0 0 0 0 Table 10.9 shows typical BRR settings in synchronous mode. Values in table 10.9 are for active (high-speed) mode. 215 Table 10.9 Typical BRR Settings and Bit Rates (Synchronous Mode) OSC (MHz) Bit Rate (bits/s) 110 250 500 1K 2.5K 5K 10K 25K 50K 100K 250K 500K 1M 2.5M Blank: Cannot be set --: Can be set, but error will result *: Continuous transmit/receive operation is not possible at this setting Note: BRR setting values are derived by the following equation. N= B: N: OSC: n: OSC 8 x 22n x B x 106 - 1 2 n -- 1 1 0 0 0 0 0 0 -- 0 N -- 249 124 249 99 49 24 9 4 -- 0* n -- 2 1 1 0 0 0 0 0 0 0 0 4 N -- 124 249 124 199 99 49 19 9 4 1 0* n -- 2 2 1 1 0 0 0 0 0 0 0 0 8 N -- 249 124 249 99 199 99 39 19 9 3 1 0* n -- -- -- -- 1 0 0 0 0 -- 0 -- -- 10 N -- -- -- -- 124 249 124 49 24 -- 4 -- -- Bit rate (bits/s) BRR baud rate generator setting (0 N 255) Value of oOSC (MHz) Baud rate generator input clock number (n = 0, 1, 2, 3) The meaning of n is shown in table 10.10. 216 Table 10.10 Relation between n and Clock SMR Setting n 0 1 2 3 Clock o o/4 o16 o/64 CKS1 0 0 1 1 CKS0 0 1 0 1 10.3.3 Operation SCI3 supports serial data communication in both asynchronous mode, where each character transferred is synchronized separately, and synchronous mode, where transfer is synchronized by clock pulses. The choice of asynchronous mode or synchronous mode, and the communication format, is made in the serial mode register (SMR), as shown in table 10.11. The SCI3 clock source is determined by bit COM in SMR and bits CKE1 and CKE0 in serial control register 3 (SCR3), as shown in table 10.12. Asynchronous Mode: * Data length: choice of 7 bits or 8 bits * Choice for the addition of a parity bit, the multiprocessor bit as well as one or two stop bits (these options determine the transmit/receive format and the character length). * Framing error (FER), parity error (PER), overrun error (OER), and break signal can be detected when data is received. * Clock source: Choice of internal clocks or an external clock When an internal clock is selected: Operates on baud rate generator clock. A clock can be output with the same frequency as the bit rate. When an external clock is selected: A clock input with a frequency 16 times the bit rate is required (internal baud rate generator is not used). Synchronous Mode: * Transfer format: 8 bits * Overrun errors can be detected when data is received. * Clock source: Choice of internal clocks or an external clock When an internal clock is selected: Operates on baud rate generator clock, and outputs a serial clock. 217 When an external clock is selected: The internal baud rate generator is not used. Operation is synchronous with the input clock. Table 10.11 SMR Settings and SCI3 Communication Format SMR Setting Bit 7: Bit 6: Bit 2: Bit 5: Bit 3: COM CHR MP PE STOP Mode 0 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 0 1 * * 1 * * 1 * 0 * 0 1 0 1 * Asynchronous 8-bit data mode (multiprocessor 7-bit data format) Synchronous mode 8-bit data Yes None Yes 7-bit data None Asynchronous mode Communication Format MultiproData Length cessor Bit 8-bit data None Parity Stop Bit Bit Length None 1 bit 2 bits Yes 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits None None None Note: * Don't care 218 Table 10.12 SMR and SCR3 Settings and Clock Source Selection SMR Bit 7: COM 0 SCR3 Bit 1: CKE1 0 Bit 0: CKE0 0 1 1 1 0 1 0 1 1 1 0 1 0 0 0 1 1 1 Synchronous mode Mode Asynchronous mode Clock Source Internal Transmit/Receive Clock Pin SCK3 Function I/O port (SCK3 pin not used) Outputs clock with same frequency as bit rate External Internal External Clock should be input with frequency 16 times the desired bit rate Outputs a serial clock Inputs a serial clock Reserved (illegal settings) 219 Continuous Transmit/Receive Operation Using Interrupts: Continuous transmit and receive operations are possible with SCI3, using the RXI or TXI interrupts. Table 10.13 explains this use of these interrupts. Table 10.13 Transmit/Receive Interrupts Interrupt RXI Flag RDRF RIE Interrupt Conditions When serial data is received normally and receive data is transferred from RSR to RDR, RDRF is set to 1. If RIE is 1 at this time, RXI is enabled and an interrupt occurs. (See figure 10.4 (a).) Remarks The RXI interrupt handling routine reads the receive data from RDR and clears RDRF to 0. Cont inuous dat a recept ion i s poss ible by performing these operations before the reception of the next serial data in RSR is completed. The TXI interrupt handling routine writes the next transmit data to TDR and clears TDRE to 0. Continuous data transmission is possible by performing these operations before the transmission of data transferred to TSR is completed. TEI indicates that, when the last bit of the TSR transmit character was sent, the next transmit data had not been written to TDR. TXI TDRE TIE When TSR empty (previous transmission complete) is detected and the transmit data set in TDR is transferred to TSR, TDRE is set to 1. If TIE is 1 at this time, TXI is enabled and an interrupt occurs. (See figure 10.4 (b).) TEI TEND TEIE When the last bit of the TSR transmit character has been sent, if TDRE is 1, then 1 is set in TEND. If TEIE is 1 at this time, TEI is enabled and an interrupt occurs. (See figure 10.4 (c).) 220 RDR RDR RSR (receiving) RXD pin RDRF = 0 RXD pin RSR (received and transferred) RDRF 1 (RXI requested if RIE = 1) Figure 10.4 (a) RDRF Setting and RXI Interrupt TDR (next transmit data) TDR TSR (transmitting) TXD pin TDRE = 0 TXD pin TSR (transmission complete, next data transferred) TDRE 1 (TXI requested if TIE = 1) Figure 10.4 (b) TDRE Setting and TXI Interrupt TDR TDR TSR (transmitting) TXD pin TEND = 0 TXD pin TSR (transmission complete) TEND 1 (TEI requested if TEIE = 1) Figure 10.4 (c) TEND Setting and TEI Interrupt 221 10.3.4 Operation in Asynchronous Mode In asynchronous communication mode, a start bit indicating the start of communication and a stop bit indicating the end of communication are added to each character that is sent/received. In this way synchronization is achieved for each character as a self-contained unit. SCI3 consists of independent transmit and receive modules, giving it the capability of full duplex communication. Both the transmit and receive modules have a double-buffer configuration, allowing data to be read or written during communication operations so that data can be transmitted and received continuously. (1) Transmit/Receive Formats: Figure 10.5 shows the general format for asynchronous serial communication. The communication line in asynchronous communication mode normally stays at the high level, in the "mark" state. SCI3 monitors the communication line, and begins serial data communication when it detects a "space" (low-level signal), which is regarded as a start bit. One character consists of a start bit (low level), transmit/receive data (in LSB-first order), a parity bit (high or low level), and finally a stop bit (high level), in this order. In asynchronous data receiving, synchronization is carried out at the falling edge of the start bit. SCI3 samples data on the 8th pulse of a clock that has 16 times the frequency of one-bit interval, so each bit of data is latched at its center. (LSB) Serial data Start bit Transmit or receive data (MSB) Parity bit 1 bit or none Stop bit 1 Mark state 1 bit 7 or 8 bits One unit of data (character or frame) 1 or 2 bits Figure 10.5 Data Format in Asynchronous Serial Communication Mode 222 Table 10.14 shows the 12 formats that can be selected in asynchronous mode. The format is selected in the serial mode register (SMR). Table 10.14 Serial Communication Formats in Asynchronous Mode SMR Settings CHR 0 0 0 0 1 1 1 1 0 0 1 1 PE 0 0 1 1 0 0 1 1 * * * * MP 0 0 0 0 0 0 0 0 1 1 1 1 STOP 0 1 0 1 0 1 0 1 0 1 0 1 1 S S S S S S S S S S S S Serial Communication Format and Frame Length 2 3 4 5 6 7 8 9 10 STOP 11 12 8-bit data 8-bit data 8-bit data 8-bit data 7-bit data 7-bit data 7-bit data 7-bit data 8-bit data 8-bit data 7-bit data 7-bit data STOP STOP STOP P P STOP STOP STOP STOP STOP P P STOP STOP STOP MPB STOP MPB STOP STOP MPB STOP MPB STOP STOP Legend: S: Start bit STOP: Stop bit P: Parity bit MPB: Multiprocessor bit Note: * Don't care 223 (2) Clock: The clock source is determined by bit COM in SMR and bits CKE1 and CKE0 in serial control register 3 (SCR3). See table 10.12 for the settings. Either an internal clock source can be used to run the built-in baud rate generator, or an external clock source can be input at pin SCK3. When an external clock source is input to pin SCK3, it should have a frequency 16 times the desired bit rate. When an internal clock source is used, SCK3 can be used as the clock output pin. The clock output has the same frequency as the serial bit rate, and is synchronized as in figure 10.6 so that the rising edge of the clock occurs in the center of each bit of transmit/receive data. Clock Serial data 0 D0 D1 D2 D3 D4 D5 D6 D7 0/1 1 1 1 character (1 frame) Figure 10.6 Phase Relation of Output Clock and Communication Data in Asynchronous Mode (8-Bit Data, Parity Bit Added, and 2 Stop Bits) (3) Data Transmit/Receive Operations SCI3 Initialization: Before data is sent or received, bits TE and RE in serial control register 3 (SCR3) must be cleared to 0, after which initialization can be performed using the procedure. Note: When modifying the operation mode, transfer format or other settings, always be sure to clear bits TE and RE first. When TE is cleared to 0, bit TDRE will be set to 1. Clearing RE does not clear the status flags RDRF, PER, FER, or OER, or alter the contents of the receive data register (RDR). When an external clock is used in asynchronous mode, do not stop the clock during operation, including during initialization. 224 Figure 10.7 shows a typical flow chart for SCI3 initialization. Start Clear TE and RE to 0 in SCR3 1 Set bits CKE1 and CKE0 1. Select the clock using serial control register 3(SCR3). Be sure to set 0 for other unused bits. When the clock output is selected in the asynchronous mode, a clock signal is output immediately after setting bits CKE1 and CKE0 appropriately. 2. Set the transmit/receive format in the serial mode register (SMR). 3. Write the value corresponding to the desired bit rate to the bit rate register (BRR). Note that this setting is not required when using an external clock. 2 Select communication format in SMR 3 Set BRR value Wait Has a 1-bit interval elapsed? Yes 4 Set bits RIE, TIE, TEIE, and MPIE in SCR3, and set TE or RE to 1 No 4. Wait for at least a 1-bit interval, then set bits RIE, TIE, TEIE, and MPIE, and set bit TE or RE in SCR3 to 1. Setting TE or RE enables SCI3 to use the TXD or RXD pin. The initial states in asynchronous mode are the mark transmit state and the idle receive state (waiting for a start bit). End Figure 10.7 Typical Flow Chart when SCI3 Is Initialized 225 Transmitting: Figure 10.8 shows a typical flow chart for data transmission. After SCI3 initialization, follow the procedure below. Start 1 Read bit TDRE in SSR TDRE = 1? Yes Write transmit data in TDR No 1. Read the serial status register (SRR), and after confirming that bit TDRE = 1, write transmit data in the transmit data register (TDR). When data is written to TDR, TDRE is automatically cleared to 0. 2 Continue data transmission? No Read bit TEND in SSR Yes 2. To continue transmitting data, first read TDRE to confirm that it is set to 1, indicating that data writing is enabled, then write the next data to TDR. When data is written to TDR, TDRE is automatically cleared to 0. No TEND = 1? Yes 3 Break output? Yes Set PDR = 0 and PCR = 1 No 3. To output a break signal when transmission ends, first set the port values PCR = 1 and PDR = 0, then clear bit TE in SCR3 to 0. Clear bit TE in SCR3 to 0 End Figure 10.8 Typical Data Transmission Flow Chart (Asynchronous Mode) 226 SCI3 operates as follows during data transmission in asynchronous mode. SCI3 monitors bit TDRE in SSR. When this bit is cleared to 0, SCI3 recognizes that there is data written in the transmit data register (TDR), which it transfers to the transmit shift register (TSR). Then TDRE is set to 1 and transmission starts. If bit TIE in SCR3 is set to 1, a TXI interrupt is requested. Serial data is transmitted from pin TXD using the communication format outlined in table 10.14. After that, it checks TDRE at the same timing which it transmits the stop bit. If TDRE is 0, data is transferred from TDR to TSR, and after the stop bit is sent, transmission of the next frame starts. If TDRE is 1, the TEND bit in SSR is set to 1, and after the stop bit is sent, the "mark state" is entered, in which 1 is continuously output. A TEI interrupt is requested in this state if bit TEIE in SCR3 is set to 1. Figure 10.9 shows a typical operation in asynchronous transmission mode. Start bit Serial data 1 0 D0 Transmit data D1 D7 1 frame TDRE Parity Stop Start bit bit bit 0/1 1 0 D0 Transmit data D1 D7 1 frame Parity Stop Mark bit bit state 0/1 1 1 TEND SCI3 TXI request TDRE cleared to 0 operation User processing Write data in TDR TXI request TEI request Figure 10.9 Typical Transmit Operation in Asynchronous Mode (8-Bit Data, Parity Bit Added, and 1 Stop Bit) Receiving: Figure 10.10 shows a typical flow chart for receiving serial data. After SCI3 initialization, follow the procedure below. 227 Start 1. Read bits OER, PER, and FER in the serial status register (SSR) to determine if a receive error has occurred. If a receive error has occurred, receive error processing is executed. 2. Read the serial status register (SSR), and after confirming that bit RDRF = 1, read received data from the receive data register (RDR). When RDR data is read, RDRF is automatically cleared to 0. 3. To continue receiving data, read bit RDRF and finish reading RDR before the stop bit of the present frame is received. When data is read from RDR, RDRF is automatically cleared to 0. 4. When a receive error occurs, read bits OER, PER, and FER in SSR to determine which error (s) occurred. After the necessary error processing, be sure to clear the above bits all to 0. Data receiving cannot be resumed while any of bits OER, PER, or FER is set to 1. When a framing error occurs, a break can be detected by reading the RXD pin value. Yes Break? No Yes PER = 1? No Clear bits OER, PER, and FER in SSR to 0 End receive error processing Parity error processing A Framing error processing 1 Read bits OER, PER, and FER in SSR OER + PER + FER = 1 No Yes 2 Read bit RDRF in SSR No RDRF = 1? Yes Read received data in RDR 4 Receive error processing Yes 3 Continue receiving? No A Clear bit RE in SCR3 to 0 End 4 Start receive error processing Yes OER = 1? No Yes FER = 1? No Overrun error processing Figure 10.10 Typical Serial Data Receiving Flow Chart in Asynchronous Mode 228 SCI3 operates as follows when receiving serial data in asynchronous mode. SCI3 monitors the communication line, and when a start bit (0) is detected it performs internal synchronization and starts receiving. The communication format for data receiving is as outlined in table 10.14. Received data is set in RSR in order of LSB to MSB, then the parity bit and stop bit(s) are received. After receiving the data, SCI3 performs the following checks: * Parity check: The number of 1s in receive data is checked to see if it matches the odd or even parity selected in bit PM of SMR. * Stop bit check: The stop bit is checked for a value of 1. If there are two stop bits, only the first bit is checked. * Status check: The RDRF bit is checked for a value of 0 to make sure received data can be transferred from RSR to RDR. If no receive error is detected by the above checks, bit RDRF is set to 1 and the received data is stored in RDR. At that time, if bit RIE in SCR3 is set to 1, an RXI interrupt is requested. If the error check detects a receive error, the appropriate error flag (OER, PER, or FER) is set to 1. RDRF retains the same value as before the data was received. If at this time bit RIE in SCR3 is set to 1, an ERI interrupt is requested. Table 10.15 gives the receive error detection conditions and the processing of received data in each case. Note: Data receiving cannot be continued while a receive error flag is set. Before continuing the receive operation it is necessary to clear the OER, FER, PER, and RDRF flags to 0. Table 10.15 Receive Error Conditions and Received Data Processing Receive Error Overrun error Framing error Parity error Abbrev. OER FER PER Detection Conditions Received Data Processing Receiving of the next data ends while Received data is not bit RDRF in SSR is still set to 1 transferred from RSR to RDR Stop bit is 0 Received data does not match the parity (odd/even) set in SMR Received data is transferred from RSR to RDR Received data is transferred from RSR to RDR 229 Figure 10.11 shows a typical SCI3 data receive operation in asynchronous mode. Start bit Serial 1 data 0 D0 Receive data D1 D7 Parity Stop Start bit bit bit 0/1 1 0 D0 Receive data D1 1 frame D7 Parity Stop bit bit 0/1 0 Mark (idle state) 1 1 frame RDRF FER SCI3 operation RXI request RDRF cleared to 0 Read RDR data Detects stop bit = 0 ERI request due to framing error Framing error handling User processing Figure 10.11 Typical Receive Operation in Asynchronous Mode (8-Bit Data, Parity Bit Added, and 1 Stop Bit) 10.3.5 Operation in Synchronous Mode In synchronous mode, data is sent or received in synchronization with clock pulses. This mode is suited to high-speed serial communication. SCI3 consists of independent transmit and receive modules, so full duplex communication is possible, sharing the same clock between both modules. Both the transmit and receive modules have a double-buffer configuration. This allows data to be written during a transmit operation so that data can be transmitted continuously, and enables data to be read during a receive operation so that data can be received continuously. 230 (1) Transmit/Receive Format: Figure 10.12 shows the general communication data format for synchronous communication. * Serial clock LSB Serial data Don't care Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 MSB Bit 7 Don't care * 8 bits One unit of communication data (character or frame) Note: * At high level except during continuous transmit/receive. Figure 10.12 Data Format in Synchronous Communication Mode In synchronous communication, data is output to the communication line during the period from one falling edge of the synchronous clock to the next falling edge. Data fixing is guaranteed at the rising edge of the synchronous clock. One character of data starts from the LSB and ends with the MSB. The communication line retains the MSB state after the MSB is output. In synchronous receive mode, SCI3 latches receive data in synchronization with the rising edge of the serial clock. The transmit/receive format is fixed at 8-bit data. No parity bit or multiprocessor bit is added in this mode. (2) Clock: Either an internal clock from the built-in baud rate generator is used, or an external clock is input at pin SCK3. The choice of clock sources is designated by bit COM in SMR and bits CKE1 and CKE0 in serial control register 3 (SCR3). See table 10.12 for details on selecting the clock source. When operation is based on an internal clock, a serial clock is output at pin SCK3. Eight clock pulses are output per character of transmit/receive data. When no transmit or receive operation is being performed, the pin is held at the high level. (3) Data Transmit/Receive Operations SCI3 Initialization: Before data is sent or received, bits TE and RE in serial control register 3 (SCR3) must be cleared to 0, after which initialization can be performed using the procedure. 231 Note: When modifying the operation mode, transfer format or other settings, always be sure to clear bits TE and RE first. When TE is cleared to 0, bit TDRE will be set to 1. Clearing RE does not clear the status flags RDRF, PER, FER, or OER, or alter the contents of the receive data register (RDR). When an external clock is used in synchronous mode, do not supply the clock during initialization. Figure 10.13 shows a typical flow chart for SCI3 initialization. Start Clear TE and RE to 0 in SCR3 1 Set bits CKE1 and CKE0 2 Select communication format in SMR 1. Select the clock using serial control register 3(SCR3). Be sure to set 0 for other unused bits. When the clock output is selected in the asynchronous mode, a clock signal is output immediately after setting bits CKE1 and CKE0 appropriately. When the clock output is selected in the synchronous mode, a clock signal is output immediately after setting bits CKE1 and CKE0 appropriately and setting bit RE to 1. 2. Set the transmit/receive format in the serial mode register (SMR). 3 Set BRR value Wait Has a 1-bit interval elapsed? Yes 4 Set bits RIE, TIE, TEIE, and MPIE in SCR3, and set TE or RE to 1 No 3. Write the value corresponding to the desired bit rate to the bit rate register (BRR). Note that this setting is not required when using an external clock. 4. Wait for at least a 1-bit interval, then set bits RIE, TIE, TEIE, and MPIE, and set bit TE or RE in SCR3 to 1. Setting TE or RE enables SCI3 to use the TXD or RXD pin. The initial states in asynchronous mode are the mark transmit state and the idle receive state (waiting for a start bit). End Note: In simultaneous transmit/receive operations, the TE and RE bits should both be cleared to 0 or set to 1 simultaneously. Figure 10.13 Typical Flow Chart when SCI3 Is Initialized 232 Transmitting: Figure 10.14 shows a typical flow chart for data transmission. After SCI3 initialization, follow the procedure below. Start 1 Read bit TDRE in SSR No TDRE = 1? Yes 1. Read the serial status register (SSR), and after confirming that bit TDRE = 1, write transmit data in the transmit data register (TDR). When data is written to TDR, TDRE is automatically cleared to 0. If clock output has been selected, after data is written to TDR, the clock is output and data transmission begins. Write transmit data in TDR Yes 2 Continue data transmission? No 2. To continue transmitting data, first read TDRE to confirm that it is set to 1, indicating that data writing is enabled; then write the next data to TDR. When data is written to TDR, TDRE is automatically cleared to 0. Read bit TEND in SSR TEND = 1? Yes No Write 0 to bit TE in SCR3 End Figure 10.14 Typical Data Transmission Flow Chart in Synchronous Mode 233 SCI3 operates as follows during data transmission in synchronous mode. SCI3 monitors bit TDRE in SSR. When this bit is cleared to 0, SCI3 recognizes that there is data written in the transmit data register (TDR), which it transfers to the transmit shift register (TSR). Then TDRE is set to 1 and transmission starts. If bit TIE in SCR3 is set to 1, a TXI interrupt is requested. If clock output is selected, SCI3 outputs eight serial clock pulses. If an external clock is used, data is output in synchronization with the clock input. Serial data is transmitted from pin TXD in order from LSB (bit 0) to MSB (bit 7). After that, it checks TDRE at the same timing which it transmits the MSB (bit 7). If TDRE is 0, data is transferred from TDR to TSR, and after the MSB (bit 7) is sent, transmission of the next frame starts. If TDRE is 1, the TEND bit in SSR is set to 1, and after the MSB (bit 7) is sent, the MSB state is maintained. A TEI interrupt is requested in this state if bit TEIE in SCR3 is set to 1. After data transmission ends, pin SCK3 is held at the high level. Note: Data transmission cannot take place while any of the receive error flags (OER, FER, PER) is set to 1. Be sure to confirm that these error flags are cleared to 0 before starting transmission. Figure 10.15 shows a typical SCI3 transmit operation in synchronous mode. Serial clock Serial data Bit 0 Bit 1 1 frame Bit 7 Bit 0 Bit 1 1 frame Bit 6 Bit 7 TDRE TEND SCI3 operation User processing TXI request TDRE cleared to 0 Write data in TDR TXI request TEI request Figure 10.15 Typical SCI3 Transmit Operation in Synchronous Mode 234 Receiving: Figure 10.16 shows a typical flow chart for receiving data. After SCI3 initialization, follow the procedure below. Start 1 Read bit OER in SSR Yes OER = 1? No 1. Read bit OER in the serial status register (SSR) to determine if an error has occurred. If an overrun error has occurred, overrun error processing is executed. 2 Read bit RDRF in SSR No RDRF = 1? Yes Read received data in RDR 4 Overrun error processing Continue receiving? No Clear bit RE in SCR3 to 0 Yes 2. Read the serial status register (SSR), and after confirming that bit RDRF = 1, read received data from the receive data register (RDR). When data is read from RDR, RDRF is automatically cleared to 0. 3. To continue receiving data, read bit RDRF and read the received data in RDR before the MSB (bit 7) of the present frame is received. When data is read from RDR, RDRF is automatically cleared to 0. 3 End Start overrun processing Overrun error processing Clear bit OER in SSR to 0 End overrun error processing 4. When an overrun error occurs, read bit OER in SSR. After the necessary error processing, be sure to clear OER to 0. Data receiving cannot be resumed while bit OER is set to 1. 4 Figure 10.16 Typical Data Receiving Flow Chart in Synchronous Mode 235 SCI3 operates as follows when receiving serial data in synchronous mode. In synchronization with the input or output of the serial clock, SCI3 initializes internally and starts receiving. Received data is set in RSR from LSB to MSB. After data has been received, SCI3 checks to confirm that the value of bit RDRF is 0 indicating that received data can be transferred from RSR to RDR. If this check passes, RDRF is set to 1 and the received data is stored in RDR. At this time, if bit RIE in SCR3 is set to 1, an RXI interrupt is requested. If an overrun error is detected, OER is set to 1 and RDRF remains set to 1. Then if bit RIE in SCR3 is set to 1, an ERI interrupt is requested. For the overrun error detection conditions and receive data processing, see table 10.15. Note: Data receiving cannot be continued while a receive error flag is set. Before continuing the receive operation it is necessary to clear the OER, FER, PER, and RDRF flags to 0. Figure 10.17 shows a typical receive operation in synchronous mode. Serial clock Serial data Bit 7 Bit 0 1 frame Bit 7 Bit 0 Bit 1 1 frame Bit 6 Bit 7 RDRF OER SCI3 operation User processing RXI request RDRF cleared to 0 Read data from RDR RXI request RDR data not read (RDRF = 1) ERI request due to overrun error Overrun error handling Figure 10.17 Typical Receive Operation in Synchronous Mode 236 Simultaneous Transmit/Receive: Figure 10.18 shows a typical flow chart for transmitting and receiving simultaneously. After SCI3 synchronization, follow the procedure below. 1. Read the serial status register (SSR), and after confirming that bit TDRE = 1, write transmit data in the transmit data register (TDR). When data is written to TDR, TDRE is automatically cleared to 0. No TDRE = 1? Yes 2 Write transmit data in TDR 2. Read the serial status register (SSR), and after confirming that bit RDRF = 1, read the received data from the receive data register (RDR). When data is read from RDR, RDRF is automatically cleared to 0. 3. To continue transmitting and receiving serial data, read bit RDRF and finish reading RDR before the MSB (bit 7) of the present frame is received. Also read bit TDRE, check that it is set to 1, and write the next data in TDR before the MSB (bit 7) of the current frame has been transmitted. When data is written to TDR, TDRE is automatically cleared to 0; and when data is read from RDR, RDRF is automatically cleared to 0. 4. When an overrun error occurs, read bit OER in SSR. After the necessary error processing, be sure to clear OER to 0. Data transmission and reception cannot take place while bit OER is set to 1. See figure 10.16 for overrun error processing. Note: When switching from transmit or receive operation to simultaneous transmit/ receive operations, first clear the TE bit and RE bit to 0, then set both these bits to 1 simultaneously. Start 1 Read bit TDRE in SSR Read bit OER in SSR Yes OER = 1? No Read RDRF in SSR No RDRF = 1? Yes Read received data in RDR 4 Continue transmitting and receiving? No Clear bits TE and RE in SCR3 to 0 End Overrun error processing Yes 3 Figure 10.18 Simultaneous Transmit/Receive Flow Chart in Synchronous Mode 237 Notes: 1. To switch from transmitting to simultaneous transmitting and receiving, first confirm that TDRE and TEND are both set to 1 and that SCI3 has finished transmitting. Next clear TE to 0. Then set both TE and RE to 1. 2. To switch from receiving to simultaneous transmitting and receiving, after confirming that SCI3 has finished receiving, clear RE to 0. Next, after confirming that RDRF and the error flags (OER FER, PER) are all 0, set both TE and RE to 1. 10.3.6 Multiprocessor Communication Function The multiprocessor communication function enables several processors to share a single serial communication line. The processors communicate in asynchronous mode using a format with an additional multiprocessor bit (multiprocessor format). In multiprocessor communication, each receiving processor is addressed by an ID code. A serial communication cycle consists of two cycles: an ID-sending cycle that identifies the receiving processor, and a data-sending cycle in which communication data is sent to the specified receiving processor. The multiprocessor bit is used to distinguish between the ID-sending cycle and the data-sending cycle. The multiprocessor bit is 1 in an ID-sending cycle, and 0 in a data-sending cycle. The transmitting processor starts by sending the ID of the receiving processor with which it wants to communicate as data with the multiprocessor bit set to 1. Next the transmitting processor sends transmit data with the multiprocessor bit cleared to 0. When a receiving processor receives data with the multiprocessor bit set to 1, it compares the data with its own ID. If the data matches its ID, the receiving processor continues to receive incoming data. If the data does not match its ID, the receiving processor skips further incoming data until it again receives data with the multiprocessor bit set to 1. Multiple processors can send and receive data in this way. Figure 10.19 shows an example of communication among different processors using a multiprocessor format. 238 Transmitting processor Communication line Receiving processor A (ID = 01) Receiving processor B (ID = 02) Receiving processor C (ID = 03) Receiving processor D (ID = 04) Serial data H'01 (MPB = 1) ID-sending cycle (receiving processor address) H'AA (MPB = 0) Data-sending cycle (data sent to receiving processor designated by ID) MPB: Multiprocessor bit Figure 10.19 Example of Interprocessor Communication Using Multiprocessor Format (Data H'AA Sent to Receiving Processor A) Four communication formats are available. Parity-bit settings are ignored when a multiprocessor format is selected. For details see table 10.14. For a description of the clock used in multiprocessor communication, see 10.3.4, Operation in Asynchronous Mode. 239 Transmitting Multiprocessor Data: Figure 10.20 shows a typical flow chart for multiprocessor serial data transmission. After SCI3 initialization, follow the procedure below. Start 1 Read bit TDRE in SSR No Yes Set bit MPBT in SSR TDRE = 1? 1. Read the serial status register (SSR), and after confirming that bit TDRE = 1, set bit MPBT (multiprocessor bit transmit) in SSR to 0 or 1, then write transmit data in the transmit data register (TDR). When data is written to TDR, TDRE is automatically cleared to 0. 2. To continue transmitting data, read bit TDRE to make sure it is set to 1, indicating that data writing is enabled. Then write the next data to TDR. When data is written to TDR, TDRE is automatically cleared to 0. 3. To output a break signal at the end of data transmission, first set the port values PCR = 1 and PDR = 0, then clear bit TE in SCR3 to 0. Write transmit data to TDR 2 Continue transmitting? No Yes Read bit TEND in SSR TEND = 1? Yes 3 Break output? Yes Set PDR = 0 and PCR = 1 No No Clear bit TE in SCR3 to 0 End Figure 10.20 Typical Multiprocessor Data Transmission Flow Chart 240 SCI3 operates as follows during data transmission using a multiprocessor format. SCI3 monitors bit TDRE in SSR. When this bit is cleared to 0, SCI3 recognizes that there is data written in the transmit data register (TDR), which it transfers to the transmit shift register (TSR). Then TDRE is set to 1 and transmission starts. If bit TIE in SCR3 is set to 1, a TXI interrupt is requested. Serial data is transmitted from pin TXD using the communication format outlined in table 10.14. Next, TDRE is checked as the stop bit is being transmitted. If TDRE is 0, data is transferred from TDR to TSR, and after the stop bit is sent, transmission of the next frame starts. If TDRE is 1, the TEND bit in SSR is set to 1, and after the stop bit is sent the output remains at 1 (mark state). A TEI interrupt is requested in this state if bit TEIE (transmit end interrupt enable) in SCR3 is set to 1. Figure 10.21 shows a typical SCI3 operation in multiprocessor communication mode. Start bit Serial data 1 0 D0 Transmit data D1 D7 Stop Start bit bit 1 0 D0 Transmit data D1 D7 Stop Mark bit state 1 1 MPB 0/1 MPB 0/1 1 frame TDRE TEND 1 frame SCI3 TXI request operation User processing TDRE cleared to 0 Write data in TDR TXI request TEI request Figure 10.21 Typical Multiprocessor Format Transmit Operation (8-Bit Data, Multiprocessor Bit Added, and 1 Stop Bit) 241 Receiving Multiprocessor Ddata: Figure 10.22 shows a typical flow chart for receiving data using a multiprocessor format. After SCI3 initialization, follow the procedure below. Start 1 2 Set bit MPIE in SCR3 to 1 Read bits OER and FER in SSR Yes OER + FER = 1? 3 No Read bit RDRF in SSR No RDRF = 1? Yes Read received data in RDR Own ID? Yes Read bits OER and FER in SSR OER + FER = 1? No 4 Read bit RDRF in SSR No RDRF = 1? Yes Read received data in RDR 5 Error processing Yes Continue receiving? No Clear bit RE in SCR3 to 0 OER = 1? End No Yes FER = 1? No Clear bits OER and FER in SSR to 0. End receive error processing No Framing error processing A Break? Yes A Start receive error processing Yes Overrun error processing Yes No 5. If a receive error occurs, read bits OER and FER in SSR to determine which error occurred. After the necessary error processing, be sure to clear the error flags to 0. Data reception cannot resume while bit OER or FER is set to 1. When a framing error occurs, a break can be detected by reading the RXD pin value. 1. Set bit MPIE in serial control register 3 (SCR3) to 1. 2. Read bits OER and FER in the serial status register (SSR) to determine if an error has occurred. If a receive error has occurred, receive error processing is executed. 3. Read the serial status register (SSR) and confirm that RDRF = 1. If RDRF = 1, read the data in the received data register (RDR) and compare it with the processor's own ID. If the received data does not match the ID, set bit MPIE to 1 again. Bit RDRF is automatically cleared to 0 when data in the received data register (RDR) is read. 4. Read SSR, check that bit RDRF = 1, then read received data from the receive data register (RDR). Figure 10.22 Typical Flow Chart for Receiving Serial Data Using Multiprocessor Format 242 Figure 10.23 gives an example of data reception using a multiprocessor format. Start bit Serial data 1 0 D0 Receive data (ID1) D1 D7 Stop Start bit MPB bit 1 1 0 D0 Receive data (data 1) D1 D7 Stop MPB bit 0 1 Mark (idle state) 1 1 frame MPIE RDRF RDR value SCI3 operation User processing RXI request MPIE cleared to 0 RDRF cleared to 0 Read data from RDR 1 frame ID1 No RXI request RDR state retained If not own ID, set MPIE to 1 again (a) Data does not match own ID Start bit Serial data 1 0 D0 Receive data (ID2) D1 D7 Stop Start MPB bit bit 1 1 0 D0 Receive data (data 2) D1 D7 Stop MPB bit 0 1 Mark (idle state) 1 1 frame MPIE RDRF RDR value SCI3 operation 1 frame ID1 RXI request MPIE cleared to 0 RDRF cleared to 0 ID2 RDRF cleared to 0 If own ID, continue receiving RXI request Data 2 User processing Read data from RDR Read data from RDR and set MPIE to 1 again (b) Data matches own ID Figure 10.23 Example of Multiprocessor Format Receive Operation (8-Bit Data, Multiprocessor Bit Added, and 1 Stop Bit) 243 10.3.7 Interrupts SCI3 has six interrupt sources: transmit end, transmit data empty, receive data full, and the three receive error interrupts (overrun error, framing error, and parity error). All share a common interrupt vector. Table 10.16 describes each interrupt. Table 10.16 SCI3 Interrupts Interrupt RXI TXI TEI ERI Interrupt Request Interrupt request due to receive data register full (RDRF) Interrupt request due to transmit data register empty (TDRE) Interrupt request due to transmit end (TEND) Interrupt request due to receive error (OER, FER, or PER) Vector Address H'0024 The interrupt requests are enabled and disabled by bits TIE and RIE of SCR3. When bit TDRE in SSR is set to 1, TXI is requested. When bit TEND in SSR is set to 1, TEI is requested. These two interrupt requests occur during data transmission. The initial value of bit TDRE is 1. Accordingly, if the transmit data empty interrupt request (TXI) is enabled by setting bit TIE to 1 in SCR3 before placing transmit data in TDR, TXI will be requested even though no transmit data has been readied. Likewise, the initial value of bit TEND is 1. Accordingly, if the transmit end interrupt request (TEI) is enabled by setting bit TEIE to 1 in SCR3 before placing transmit data in TDR, TEI will be requested even though no data has been transmitted. These interrupt features can be used to advantage by programming the interrupt handler to move the transmit data into TDR. When this technique is not used, the interrupt enable bits (TIE and TEIE) should not be set to 1 until after TDR has been loaded with transmit data, to avoid unwanted TXI and TEI interrupts. When bit RDRF in SSR is set to 1, RXI is requested. When any of SSR bits OER, FER, or PER is set to 1, ERI is requested. These two interrupt requests occur during the receiving of data. Details on interrupts are given in 3.3, Interrupts. 244 10.3.8 Application Notes When using SCI3, attention should be paid to the following matters. Relation between Bit TDRE and Writing Data to TDR: Bit TDRE in the serial status register (SSR) is a status flag indicating that TDR does not contain new transmit data. TDRE is automatically cleared to 0 when data is written to TDR. When SCI3 transfers data from TDR to TSR, bit TDRE is set to 1. Data can be written to TDR regardless of the status of bit TDRE. However, if new data is written to TDR while TDRE is cleared to 0, assuming the data held in TDR has not yet been shifted to TSR, it will be lost. For this reason, it is recommended for securing serial data transmission that writing transmit data to TDR should be performed only once (not two or more times), always after confirming that bit TDRE is set to 1. Operation when Multiple Receive Errors Occur at the Same Time: When two or more receive errors occur at the same time, the status flags in SSR are set as shown in table 10.17. If an overrun error occurs, data is not transferred from RSR to RDR, and receive data is lost. Table 10.17 SSR Status Flag States and Transfer of Receive Data Receive Data Transfer (RSR RDR) Receive Error Status x Overrun error Framing error Parity error x x x Overrun error + framing error Overrun error + parity error Framing error + parity error Overrun error + framing error + parity error SSR Status Flags RDRF* OER 1 0 0 1 1 0 1 1 0 0 1 1 0 1 FER 0 1 0 1 0 1 1 PER 0 0 1 0 1 1 1 : Receive data transferred from RSR to RDR x : Receive data not transferred from RSR to RDR Note: * RDRF keeps the same state as before the data was received. 245 Break Detection and Processing: Break signals can be detected by reading the RXD pin directly when a framing error (FER) is detected. In the break state the input from the RXD pin consists of all 0s, so FER is set and the parity error flag (PER) may also be set. In the break state SCI3 continues to receive, so if the FER bit is cleared to 0 it will be set to 1 again. Sending a Mark or Break Signal: When the TXD bit in PMR6 is cleared to 0, the TXD pin becomes an I/O port, the level and direction (input or output) of which are determined by the PDR and PCR bits. This feature can be used to place the TXD pin in the mark state or to send a break signal. To place the serial communication line in the mark (1) state before TE is set to 1, set the PDR and PCR bits both to 1. The TXD pin becomes an I/O port outputting the value 1. To send a break signal during transmission, set the PCR bit to 1 and clear the PDR bit to 0, then clear the TXD bit in PMR6 to 0. When the TXD bit in PMR6 is cleared to 0, the TXD pin becomes an I/O port outputting 0, regardless of the current transmission status. Receive Error Flags and Transmit Operation (Sysnchronous Mode Only): When a receive error flag (ORER, PER, or FER) is set to 1, SCI3 will not start transmitting even if TDRE is cleared to 0. Be sure to clear the receive error flags to 0 when starting to transmit. Note that clearing RE to 0 does not clear the receive error flags. Receive Data Sampling Timing and Receive Margin in Asynchronous Mode: In asynchronous mode SCI3 operates on a base clock with 16 times the bit rate frequency. In receiving, SCI3 synchronizes internally with the falling edge of the start bit, which it samples on the base clock. Receive data is latched at the rising edge of the eighth base clock pulse. See figure 10.24. 246 16 clock cycles 8 clock cycles Internal base clock 0 7 15 0 7 15 0 Receive data (RXD) Start bit D0 D1 Synchronization sampling timing Data sampling timing Figure 10.24 Receive Data Sampling Timing in Asynchronous Mode The receive margin in asynchronous mode can therefore be derived from the following equation. 1 D - 0.5 M = (0.5 - )- - (L - 0.5) F x 100% ...................... Equation (1) 2N N M: N: D: L: F: Receive margin (%) Ratio of clock frequency to bit rate (N = 16) Clock duty cycle (D = 0.5 to 1) Frame length (L = 9 to 12) Absolute value of clock frequency error In equation (1), if F (absolute value of clock frequency error) = 0 and D (clock duty cycle) = 0.5, the receive margin is 46.875% as given by equation (2) below. When D = 0.5 and F = 0, M = {0.5 - 1/(2 x 16)} x 100% = 46.875% ...................................... Equation (2) This value is theoretical. In actual system designs a margin of from 20 to 30 percent should be allowed. 247 Relationship between Bit RDRF and Reading RDR: While SCI3 is receiving, it checks the RDRF flag. If the RDRF flag is cleared to 0 when the reception of one frame of data is completed, data reception ends normally. If RDRF is set to 1, an overrun error occurs. RDRF is automatically cleared to 0 when the contents of RDR are read. If RDR is read more than once, the second and later reads will be performed with RDRF cleared to 0. Note that when RDR is read while RDRF is 0, data from the next frame may be read if this reading operation is carried out at the same time that the reception of the next frame is completed. This is illustrated in figure 10.25. Frame 1 Frame 2 Frame 3 Communication line Data 1 Data 2 Data 3 RDRF RDR Data 1 (A) RDR read Data 2 (B) RDR read At (A), data 1 is read. At (B), data 2 is read. Figure 10.25 Relationship between Data and RDR Read Timing To avoid the situation described above, RDR reading should be carried out only once (not two or more times) after confirming that bit RDRF is set to 1. When reading RDR more than once, be sure to copy any data read for the first time to RAM, for example, and use the copied data. Also note that RDR reading should be carried out with a safe margin just before reception of the next frame is completed. More concretely, RDR reading should be completed before transferring bit 7 in the synchronous mode or before transferring the stop bit in the asynchronous mode. 248 Section 11 DTMF Generator 11.1 Overview The H8/3627 Series has an on-chip dual-tone multifrequency (DTMF) generator that can generate DTMF signals. A DTMF signal accesses a telephone switching system by a pair of sine waves. Figure 11.1 shows the frequency matrix. The DTMF generator generates frequencies corresponding to the numbers and symbols on the keypad of a telephone set or facsimile machine. 1 2 3 A R1 (697 Hz) 4 5 6 B R2 (770 Hz) 7 8 9 C R3 (852 Hz) 0 # D R4 (941 Hz) C1 (1,209 Hz) C2 (1,336 Hz) C3 (1,477 Hz) Figure 11.1 DTMF Frequencies C4 (1,633 Hz) 249 11.1.1 Features Features of the DTMF generator are as follows. * Generates sine waves with DTMF frequencies from the system clock input at the OSC pins (f OSC ) The OSC clock (1.2 MHz to 10 MHz, selectable in 400-kHz steps) is divided to generate a 400-kHz clock. Input to a feedback loop with a modified programmable divider and sine-wave counter, this clock is used to generate sine waves with the DTMF frequencies. * Stable sine-wave output with low distortion Sine waves are output from a high-precision resistor-ladder-type D/A converter. Each cycle is divided into 32 segments to give a stable waveform with low distortion. * Composite or single waveform output Register settings can select combined row-and-column-group output, or independent rowgroup or column-group output. 250 11.1.2 Block Diagram Figure 11.2 shows a block diagram of the DTMF generator. DTLR (1.2 MHz to 10 MHz, selectable in 400-kHz steps) fOSC Clock counter 400 kHz Row section D/A sine-wave counter Feedback TONED VTref Column section D/A sine-wave counter Feedback Legend: DTLR: DTMF load register DTCR: DTMF control register Modified programmable divider DTCR Modified programmable divider Internal data bus 251 Figure 11.2 DTMF Generator Block Diagram 11.1.3 Pin Configuration Table 11.1 shows the pins assigned to the DTMF generator. Table 11.1 Pin Configuration Name DTMF output reference level power supply pin DTMF signal output pin Abbrev. VT ref TONED I/O -- Output Function Reference level voltage for DTMF output DTMF signal output 11.1.4 Register Configuration Table 11.2 shows the register configuration of the DTMF generator. Table 11.2 Register Configuration Name DTMF control register DTMF load register Abbrev. DTCR DTLR R/W R/W R/W Initial Value H'40 H'E0 Address H'FFB2 H'FFB3 252 11.2 11.2.1 Bit Register Descriptions DTMF Control Register (DTCR) 7 DTEN 6 -- 1 -- 5 CLOE 0 R/W 4 RWOE 0 R/W 3 CLF1 0 R/W 2 CLF0 0 R/W 1 RWF1 0 R/W 0 RWF0 0 R/W Initial value Read/Write 0 R/W DTCR is an 8-bit read/write register that enables the DTMF generator, enables row and column output, and selects the output frequencies. Upon reset, DTCR is initialized to H'40. Bit 7--DTMF Generator Enable (DTEN): Bit 7 enables or disables operation of the DTMF generator. Bit 7: DTEN 0 1 Description DTMF generator is halted DTMF generator operates (initial value) Bit 6--Reserved Bit: Bit 6 is reserved: it is always read as 1, and cannot be modified. Bit 5--Column Output Enable (CLOE): Bit 5 enables or disables DTMF column signal output. Bit 5: CLOE 0 1 Description DTMF column signal output is disabled (high-impedance) DTMF column signal output is enabled (initial value) Bit 4--Row Output Enable (RWOE): Bit 4 enables or disables DTMF row signal output. Bit 4: RWOE 0 1 Description DTMF row signal output is disabled (high-impedance) DTMF row signal output is enabled (initial value) 253 Bits 3 and 2--DTMF Column Signal Output Frequency 1 and 0 (CLF1, CLF0): Bits 3 and 2 select the DTMF column signal frequency (C1 to C4). Bit 3: CLF1 0 Bit 2: CLF0 0 1 1 0 1 Description DTMF column signal output frequency: 1209 Hz (C1) (initial value) DTMF column signal output frequency: 1336 Hz (C2) DTMF column signal output frequency: 1447 Hz (C3) DTMF column signal output frequency: 1633 Hz (C4) Bits 1 and 0--DTMF Row Signal Output Frequency 1 and 0 (RWF1, RWF0): Bits 1 and 0 select the DTMF row signal frequency (R1 to R4). Bit 1: RWF1 0 Bit 0: RWF0 0 1 1 0 1 Description DTMF row signal output frequency: 697 Hz (R1) (initial value) DTMF row signal output frequency: 770 Hz (R2) DTMF row signal output frequency: 852 Hz (R3) DTMF row signal output frequency: 941 Hz (R4) 254 11.2.2 Bit DTMF Load Register (DTLR) 7 -- 6 -- 1 -- 5 -- 1 -- 4 DTL4 0 R/W 3 DTL3 0 R/W 2 DTL2 0 R/W 1 DTL1 0 R/W 0 DTL0 0 R/W Initial value Read/Write 1 -- DTLR is an 8-bit read/write register that specifies the ratio by which the clock frequency at the OSC pins is divided for input to the DTMF generator. Upon reset, DTLR is initialized to H'E0. Bits 7 to 5--Reserved Bits: Bits 7 to 5 are reserved: they are always read as 1, and cannot be modified. Bits 4 to 0--OSC Clock Division Ratio 4 to 0 (DTL4 to DTL0): Bits 4 to 0 specify a division ratio of the OSC clock frequency which will generate a 400-kHz clock for input to the DTMF generator. The ratio is set as a counter value from 3 to 25, corresponding to OSC clock frequencies of 1.2 to 10 MHz (in 400-kHz steps). Description Bit 4: DTL4 0 Bit 3: DTL3 0 Bit 2: DTL2 0 Bit 1: DTL1 0 Bit 0: DTL0 0 1 1 0 1 1 : 1 : 1 : 0 0 : 0 1 1 Note: * Don't care * 0 : 1 * * Division Ratio Illegal setting Illegal setting Illegal setting 3 4 : 25 Illegal setting Illegal setting 1.2 MHz 1.6 MHz : 10 MHz OSC Clock Frequency (initial value) These bits must be set to the correct value. Normal DTMF signal output frequencies will not be obtained if these bits are set to a value not matching the clock input at the OSC pins. Operation is not guaranteed if these bits are set to a value other than 3 to 25. 255 11.3 11.3.1 Operation Output Waveform The DTMF generator outputs a row-group or column-group sine wave (DTMF signal) or a combined row-column waveform at the TONED pin. These signals are generated by a highprecision resistor-ladder-type D/A converter circuit. The output frequency is selected by DTCR. Figure 11.3 shows an equivalent circuit for the TONED output. Figure 11.4 shows the output waveform of an independent row-group or column-group signal. One cycle of the output is divided into 32 segments, giving a stable output with low distortion. Control VTref Output control GND Row TONED Column Figure 11.3 Equivalent Circuit for TONED Output VTref 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 GND Time slot Figure 11.4 TONED Output Waveform (Independent Row- or Column-Group Output) 256 Table 11.3 indicates the frequency deviation between the DTMF signals output by the DTMF generator and the nominal (standard) signal values. Table 11.3 Frequency Deviation of DTMF Signals from Nominal Signals Symbol R1 R2 R3 R4 C1 C2 C3 C4 Standard Signal Frequency (Hz) 697 770 852 941 1209 1336 1477 1633 DTMF Signal Output (Hz) 694.44 769.23 851.06 938.97 1212.12 1333.33 1481.48 1639.34 Frequency Deviation (%) -0.37 -0.10 -0.11 -0.22 0.26 -0.20 0.30 0.39 11.3.2 Operation Flow The procedure for using the DTMF generator is given below. 1. Set the OSC clock division ratio in DTLR to match the frequency of the connected system clock oscillator (1.2 MHz to 10 MHz in 400-kHz steps). 2. Select a row (R1 to R4) and/or column (C1 to C4) frequency with bits CLF1, CLF0, RWF1, and RWF0 in DTCR. 3. Select row and/or column output with the CLOE and RWOE bits in DTCR, and set the DTEN bit to 1 to enable the DTMF generator. This procedure outputs the selected DTMF signal from the TONED pin. 257 11.4 Typical Use Figure 11.5 shows an example of the use of the DTMF generator. 24 k TONED 2 k 20 VTref H8/3637 100 k +0.47 F 11 P14 360 k MUTE 2SC458 Vref1 19 DTMF HA16808ANT Note: Numbers at ends of signal lines are pin numbers of HA16808ANT. Figure 11.5 Connection to HA16808 ANT 11.5 Application Notes When using the DTMF generator, note the following point: Be sure that the DTLR setting (DTL4 to DTL0) matches the system clock frequency at the OSC pins. Normal DTMF signal output frequencies will not be obtained unless the DTLR setting matches the OSC frequency. 258 Section 12 A/D Converter 12.1 Overview The H8/3627 Series includes on-chip a resistance-ladder-based successive-approximation analogto-digital converter, and can convert up to two channels of analog input. 12.1.1 Features The A/D converter has the following features. * * * * * * 8-bit resolution 2 input channels Conversion time: approx. 12.4 s per channel (at 5 MHz operation) Built-in sample-and-hold function Interrupt requested on completion of A/D conversion A/D conversion can be started by external trigger input 259 12.1.2 Block Diagram Figure 12.1 shows a block diagram of the A/D converter. ADTRG AMR AN6 AN7 V CC + Comparator - VCC VSS Reference voltage V SS ADRR Legend: AMR: A/D mode register ADSR: A/D start register ADRR: A/D result register IRRAD: A/D converter interrupt request flag Internal data bus IRRAD Multiplexer ADSR Control logic Figure 12.1 Block Diagram of the A/D Converter 12.1.3 Pin Configuration Table 12.1 shows the A/D converter pin configuration. Table 12.1 Name Power supply pin Ground pin Analog input pin 6 Analog input pin 7 External trigger input pin 260 Pin Configuration Abbrev. VCC VSS AN 6 AN 7 ADTRG I/O Input Input Input Input Input Function Power supply Ground and reference voltage Analog input channel 6 Analog input channel 7 External trigger input for starting A/D conversion 12.1.4 Register Configuration Table 12.2 shows the A/D converter register configuration. Table 12.2 Register Configuration Name A/D mode register A/D start register A/D result register Abbrev. AMR ADSR ADRR R/W R/W R/W R Initial Value H'10 H'7F Undefined Address H'FFC4 H'FFC6 H'FFC5 12.2 12.2.1 Bit Register Descriptions A/D Result Register (ADRR) 7 ADR7 6 ADR6 5 ADR5 4 ADR4 3 ADR3 2 ADR2 1 ADR1 0 ADR0 Initial value Read/Write Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R R R R R R R R The A/D result register (ADRR) is an 8-bit read-only register for holding the results of analog-todigital conversion. ADRR can be read by the CPU at any time, but the ADRR values during A/D conversion are undefined. After A/D conversion is complete, the conversion result is stored in ADRR as 8-bit data; this data is held in ADRR until the next conversion operation starts. ADRR is not cleared on reset. 261 12.2.2 Bit A/D Mode Register (AMR) 7 CKS 6 TRGE 0 R/W 5 CKS1 0 R/W 4 -- 1 -- 3 CH3 0 R/W 2 CH2 0 R/W 1 CH1 0 R/W 0 CH0 0 R/W Initial value Read/Write 0 R/W AMR is an 8-bit read/write register for specifying the A/D conversion speed, external trigger option, and the analog input pins. Upon reset, AMR is initialized to H'10. Bit 7--Clock Select (CKS): Bits CKS and CKS1 select the A/D conversion speed. Conversion Time Bit 5: CKS1 0 Bit 7: CKS 0 1 1 0 1 Conversion Period Reserved (initial value) 124/o 62/o 31/o o = 2 MHz -- 62 s 31 s 15.5 s o = 5 MHz -- 24.8 s 12.4 s --* Note: * Operation is not guaranteed if the conversion time is less than 12.4 s. Set the bits to get a value of at least 12.4 s. Bit 6--External Trigger Select (TRGE): Bit 6 enables or disables the start of A/D conversion by external trigger input. Bit 6: TRGE 0 1 Description Disables start of A/D conversion by external trigger (initial value) Enables start of A/D conversion by rising or falling edge of external trigger at pin ADTRG* Note: * The external trigger (ADTRG) edge is selected by bit IEG4 of the interrupt edge select register (IEGR). See 3.3.2 for details. Bit 5--Clock Select 1 (CKS1): Bits CKS and CKS1 select the A/D conversion speed. See bit 7, clock select (CKS) for details. Bit 4--Reserved Bit: Bit 4 is reserved; it is always read as 1, and cannot be modified. 262 Bits 3 to 0--Channel Select 3 to 0 (CH3 to CH0): Bits 3 to 0 select the analog input channel. The channel selection should be made while bit ADSF is cleared to 0. Bit 3: CH3 0 Bit 2: CH2 0 1 1 0 Bit 1: CH1 * * 0 1 Bit 0: CH0 * * * 0 1 1 Note: * Don't care * * Analog Input Channel No channel selected Reserved Reserved AN 6 AN 7 Reserved (initial value) 12.2.3 Bit A/D Start Register (ADSR) 7 ADSF 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 -- 1 -- 2 -- 1 -- 1 -- 1 -- 0 -- 1 -- Initial value Read/Write 0 R/W The A/D start register (ADSR) is an 8-bit read/write register for starting and stopping A/D conversion. A/D conversion is started by writing 1 to the A/D start flag (ADSF) or by input of the designated edge of the external trigger signal, which also sets ADSF to 1. When conversion is complete, the converted data is set in the A/D result register (ADRR), and at the same time ADSF is cleared to 0. Bit 7--A/D Start Flag (ADSF): Bit 7 controls and indicates the start and end of A/D conversion. Bit 7: ADSF 0 Description Read access Write access 1 Read access Write access Indicates the completion of A/D conversion. Stops A/D conversion. Indicates A/D conversion in progress. Starts A/D conversion. (initial value) Bits 6 to 0--Reserved Bits: Bits 6 to 0 are reserved; they are always read as 1, and cannot be modified. 263 12.3 12.3.1 Operation A/D Conversion Operation The A/D converter operates by successive approximations, and yields its conversion result as 8-bit data. A/D conversion begins when software sets the A/D start flag (bit ADSF) to 1. Bit ADSF keeps a value of 1 during A/D conversion, and is cleared to 0 automatically when conversion is complete. The completion of conversion also sets bit IRRAD in interrupt request register 2 (IRR2) to 1. An A/D conversion end interrupt is requested if bit IENAD in interrupt enable register 2 (IENR2) is set to 1. If the conversion time or input channel needs to be changed in the A/D mode register (AMR) during A/D conversion, bit ADSF should first be cleared to 0, stopping the conversion operation, in order to avoid malfunction. 12.3.2 Start of A/D Conversion by External Trigger Input The A/D converter can be made to start A/D conversion by input of an external trigger signal. External trigger input is enabled at pin ADTRG when bit IRQ4 in port mode register 2 for the I/O port (PMR2) is set to 1, and bit TRGE in AMR is set to 1. Then when the input signal edge designated in bit IEG4 of the IRQ edge select register (IEGR) is detected at pin ADTRG, bit ADSF in ADSR will be set to 1, starting A/D conversion. Figure 12.2 shows the timing. o Pin ADTRG (when bit IEG4 = 0) ADSF A/D conversion Figure 12.2 External Trigger Input Timing 264 12.4 Interrupts When A/D conversion ends (ADSF changes from 1 to 0), bit IRRAD in interrupt request register 2 (IRR2) is set to 1. A/D conversion end interrupts can be enabled or disabled by means of bit IENAD in interrupt enable register 2 (IENR2). For further details see 3.3, Interrupts. 12.5 Typical Use An example of how the A/D converter can be used is given below, using channel 6 (pin AN6) as the analog input channel. Figure 12.3 shows the operation timing. 1. Bits CH3 to CH0 of the A/D mode register (AMR) are set to 1010, making pin AN6 the analog input channel. A/D interrupts are enabled by setting bit IENAD to 1, and A/D conversion is started by setting bit ADSF to 1. 2. When A/D conversion is complete, bit IRRAD is set to 1, and the A/D conversion result is stored in the A/D result register (ADRR). At the same time ADSF is cleared to 0, and the A/D converter goes to the idle state. 3. Bit IENAD = 1, so an A/D conversion end interrupt is requested. 4. The A/D interrupt handling routine starts. 5. The A/D conversion result is read and processed. 6. The A/D interrupt handling routine ends. If ADSF is set to 1 again afterward, A/D conversion starts and steps 2 through 6 take place. Figures 12.4 and 12.5 show flow charts of procedures for using the A/D converter. 265 266 Set * A/D conversion starts Set * Set * Idle A/D conversion (1) Idle A/D conversion (2) Idle Read conversion result A/D conversion result (1) Read conversion result A/D conversion result (2) Interrupt (IRRAD) IENAD ADSF Channel 4 (AN4) operation state ADRR Figure 12.3 Typical A/D Converter Operation Timing Note: * ( ) indicates instruction execution by software. Start Set A/D conversion speed and input channel Disable A/D conversion end interrupt Start A/D conversion Read ADSR No ADSF = 0? Yes Read ADRR data Yes Perform A/D conversion? No End Figure 12.4 Flow Chart of Procedure for Using A/D Converter (1) (Polling by Software) 267 Start Set A/D conversion speed and input channels Enable A/D conversion end interrupt Start A/D conversion A/D conversion end interrupt? No Yes Clear bit IRRAD to 0 in IRR2 Read ADRR data Yes Perform A/D conversion? No End Figure 12.5 Flow Chart of Procedure for Using A/D Converter (2) (Interrupts Used) 12.6 Application Notes * Data in the A/D result register (ADRR) should be read only when the A/D start flag (ADSF) in the A/D start register (ADSR) is cleared to 0. * Changing the digital input signal at an adjacent pin during A/D conversion may adversely affect conversion accuracy. 268 Section 13 Power Supply Circuit 13.1 Overview The H8/3627 Series incorporates an internal power supply step-down circuit. Use of this circuit enables the internal power supply to be fixed at a constant level of approximately 3.0 V, independent of the voltage of the power supply connected to the external VCC pin. As a result, rise of the current consumption when an external power supply is used at 3.0 V or above can be held down. 13.2 Configuration of the Internal Power Supply Step-Down Circuit Connect the external power supply to the VCC pin, and connect a capacitance of approximately 0.1 F between CV CC and V SS , as shown in figure 13.1. Use without the capacitance may cause malfunction. Note: In the external circuit interface, the external power supply voltage connected to VCC and the GND potential connected to VSS are the reference levels. For example, for port input/output levels, the V CC level is the reference for the high level, and the VSS level is that for the low level. 269 VCC Step-down circuit CVCC Stabilization capacitance (approx. 0.1 F) C Internal logic Internal power supply VSS C: Capacitor with the standard power supply circuit configuration Figure 13.1 Power Supply Connection when Internal Step-Down Circuit is Used 270 Section 14 Electrical Characteristics 14.1 Absolute Maximum Ratings Table 14.1 lists the absolute maximum ratings. Table 14.1 Absolute Maximum Ratings Item Power supply voltage Reference level supply voltage Programming voltage Input voltage Ports other than port B Port B Operating temperature Storage temperature Symbol VCC, CV CC VT ref VPP Vin AVin Topr Tstg Value -0.3 to +7.0 -0.3 to VCC +0.3 -0.3 to +13.0 -0.3 to VCC +0.3 -0.3 to VCC +0.3 -20 to +75 -55 to +125 Unit V V V V V C C Notes 1 1 1 1 1 1 1 Note: 1. Permanent damage may occur to the chip if maximum ratings are exceeded. Normal operation should be under the conditions specified in Electrical Characteristics. Exceeding these values can result in incorrect operation and reduced reliability. 271 14.2 14.2.1 Electrical Characteristics Power Supply Voltage and Operating Range The power supply voltage and operating range are indicated by the shaded region in the figures below. Note: Caution is required during development, since the guaranteed operating ranges of the chip and development tools are different. Power Supply Voltage vs. Oscillator Frequency Range 10.0 f OSC (MHz) 32.768 5.0 fw (kHz) 2.2* 2.7 4.0 5.5 VCC (V) 2.0 2.2* 4.0 5.5 VCC (V) * Active mode (high and medium speeds) * Sleep mode Note: * The oscillation start voltage is 2.5 V. * All operating modes 272 Power Supply Voltage vs. Clock Frequency Range 5.0 oSUB (kHz) 2.2 2.7 4.0 5.5 VCC (V) 16.384 o (MHz) 2.5 8.192 4.096 0.5 2.2 4.0 5.5 VCC (V) * Active mode (high speed) * Sleep mode (except CPU) * Subactive mode * Subsleep mode (except CPU) * Watch mode (except CPU) 625.0 500.0 o (kHz) 312.5 62.5 2.7 4.0 5.5 VCC (V) * Active mode (medium speed) Analog Power Supply Voltage vs. A/D Converter Operating Range 5.0 o (MHz) 625.0 500.0 2.5 o (kHz) 2.2 2.7 4.0 5.5 V CC (V) 312.5 0.5 62.5 2.7 4.0 5.5 VCC (V) * Active (high speed) mode * Sleep mode * Active (medium speed) mode 273 14.2.2 DC Characteristics Table 14.2 lists the DC characteristics. Table 14.2 DC Characteristics VCC = 2.2 V to 5.5 V, VSS = 0.0 V, Ta = -20 to +75C, including subactive mode, unless otherwise indicated. Item Input high voltage Symbol VIH Applicable Pins RES, WKP0 to WKP7, IRQ0 to IRQ4, TMIF, TMIG, SCK1, SCK3, ADTRG SI 1, RXD Min 0.8 V CC 0.9 V CC Typ -- -- Max VCC +0.3 VCC +0.3 Unit V Test Condition VCC = 2.7 V to 5.5 V Note 0.7 V CC 0.8 V CC -- -- -- -- -- VCC +0.3 VCC +0.3 VCC +0.3 VCC +0.3 VCC +0.3 V VCC = 2.7 V to 5.5 V OSC1 VCC -0.5 VCC -0.3 V VCC = 2.7 V to 5.5 V P10 to P17, P20 to P27, P50 to P57, P60 to P67, P70 to P77, P80 to P87, PA 1 to PA3, PB 6, PB7 Input low voltage VIL RES, WKP0 to WKP7, IRQ0 to IRQ4, TMIF, TMIG, SCK1, SCK3, ADTRG SI 1, RXD 0.7 V CC V VCC = 2.7 V to 5.5 V 0.8 V CC -- VCC +0.3 -0.3 -- 0.2 V CC V VCC = 2.7 V to 5.5 V -0.3 -- 0.1 V CC -0.3 -0.3 -- -- -- -- 0.3 V CC 0.2 V CC 0.5 0.3 V VCC = 2.7 V to 5.5 V OSC1 -0.3 -0.3 V VCC = 2.7 V to 5.5 V Note: Connect pin TEST to VSS . 274 Table 14.2 DC Characteristics (cont) VCC = 2.2 V to 5.5 V, VSS = 0.0 V, Ta = -20 to +75C, including subactive mode, unless otherwise indicated. Item Input low voltage Symbol VIL Applicable Pins P10 to P17, P20 to P27, P50 to P57, P60 to P67, P70 to P77, P80 to P87, PA 1 to PA3, PB 6, PB7 P10 to P17, P20 to P26, P50 to P57, P60 to P67, P70 to P77, P80 to P87, PA 1 to PA3, P50 to P57, P60 to P67, P70 to P77, P80 to P87, PA 1 to PA3, P10 to P17, P20 to P26 Min -0.3 Typ -- Max 0.3 V CC Unit V Test Condition VCC = 2.7 V to 5.5 V Note -0.3 -- 0.2 V CC Output high voltage VOH VCC - 1.0 -- -- V VCC = 4.0 V to 5.5 V -I OH = 1.0 mA VCC = 4.0 V to 5.5 V -I OH = 0.5 mA -I OH = 0.1 mA VCC - 0.5 -- -- VCC - 0.5 -- -- -- -- 0.5 V Output low voltage VOL IOL = 0.4 mA -- -- -- -- -- -- 1.5 0.6 0.5 VCC = 4.0 V to 5.5 V IOL = 10 mA VCC = 4.0 V to 5.5 V IOL = 1.6 mA IOL = 0.4 mA 275 Table 14.2 DC Characteristics (cont) VCC = 2.2 V to 5.5 V, VSS = 0.0 V, Ta = -20 to +75C, including subactive mode, unless otherwise indicated. Item Input leakage current Symbol |IIL| Applicable Pins RES, P27 Min -- -- OSC1, P10 to P17, P20 to P26, P50 to P57, P60 to P67, P70 to P77, P80 to P87, PA 1 to PA3, PB 6, PB7 Pull-up MOS current -I P P10 to P17, P20 to P26 P50 to P57, P60 to P67 CIN All input pins except power supply pins RES P27 -- Typ -- -- -- Max 20 1 1 Unit Test Condition VIN = 0.5 V to VCC - 0.5 V VIN = 0.5 V to VCC - 0.5 V Note 3 2 A A 50 -- -- -- 35 -- 300 -- 15 A VCC = 5 V, VIN = 0 V VCC = 2.7 V, VIN = 0 V Reference value Input capacitance pF f = 1 MHz, VIN = 0 V, Ta = 25C 3 -- -- -- -- 80 50 Notes: 2. Applies to HD6433622, HD6433623, HD6433624, HD6433625, HD6433626, and HD6433627. 3. Applies to HD6473627. 276 Table 14.2 DC Characteristics (cont) VCC = 2.2 V to 5.5 V, VSS = 0.0 V, Ta = -20 to +75C, including subactive mode, unless otherwise indicated. Item Symbol Applicable Pins Min VCC -- Typ 6 Max 9 Unit mA Test Condition Active mode (high speed), VCC = 5 V, fosc = 10 MHz Active mode (medium speed), VCC = 5 V, fosc = 10 MHz VCC = 5 V, fosc = 10 MHz VCC = 2.7 V, 32-kHz crystal oscillator (o SUB = ow/2) VCC = 2.7 V, 32-kHz crystal oscillator (o SUB = ow/8) VCC = 2.7 V, 32-kHz crystal oscillator (o SUB = ow/2) VCC = 2.7 V, 32-kHz crystal oscillator 32-kHz crystal oscillator not used Notes 4, 5 Active mode current IOPE1 dissipation IOPE2 VCC -- 2 4 mA 4, 5 Sleep mode current ISLEEP dissipation Subactive mode current dissipation ISUB VCC VCC -- -- 3.5 12 6 30 mA A 4, 5 4, 5 -- 6 -- A Reference value 4, 5 4, 5 Subsleep mode current dissipation ISUBSP VCC -- 5 15 A Watch mode current IWATCH dissipation Standby mode current dissipation RAM data retaining voltage ISTBY VRAM VCC VCC VCC -- -- 2 -- -- -- 6 5 -- A A V 4, 5 4, 5 Notes: 4. Pin states during current measurement are shown below. Mode Active mode (high and mediumspeed) Sleep mode Subactive mode Subsleep mode Watch mode Standby mode Other Pins VCC VCC VCC VCC VCC VCC Internal State Operates Only timer operates Operates Only timer operates, CPU stops Only time-base clock operates, CPU stops CPU and timers all stop System clock oscillator: Crystal Subclock oscillator: Pin X1 = VCC System clock oscillator: Crystal Subclock oscillator: Crystal Oscillator Pins System clock oscillator: Crystal Subclock oscillator: Pin X1 = VCC 5. Excludes current in pull-up MOS transistors and output buffers. 277 Table 14.2 DC Characteristics (cont) VCC = 2.2 V to 5.5 V, VSS = 0.0 V, Ta = -20 to +75C, including subactive mode, unless otherwise indicated. Item Allowable output low current (per pin) Symbol IOL Applicable Pins Output pins except in ports 1 and 2 Ports 1 and 2 All output pins Allowable output low current (total) IOL Output pins except in ports 1 and 2 Ports 1 and 2 All output pins Allowable output high current (per pin) Allowable output high current (total) -I OH -I OH All output pins Min -- -- -- -- -- -- -- -- All output pins -- -- Typ -- -- -- -- -- -- -- -- -- -- Max 2 10 0.5 40 80 20 2 0.2 15 10 mA VCC = 4.0 V to 5.5 V mA VCC = 4.0 V to 5.5 V mA VCC = 4.0 V to 5.5 V VCC = 4.0 V to 5.5 V Unit mA Test Condition VCC = 4.0 V to 5.5 V VCC = 4.0 V to 5.5 V 278 14.2.3 AC Characteristics Table 14.3 lists the control signal timing, and tables 14.4 and 14.5 list the serial interface timing. Table 14.3 Control Signal Timing VCC = 2.2 V to 5.5 V, VSS = 0.0 V, Ta = -20 to +75C, including subactive mode, unless otherwise specified. Item Symbol Applicable Pins OSC1, OSC2 Min 2 2 OSC1, OSC2 100 200 tcyc 2 -- fW tW tsubcyc X1, X2 X1, X2 -- -- 2 2 trc OSC1, OSC2 -- -- trc tCPH X1, X2 OSC1 -- 40 80 tCPL OSC1 40 80 tCPr -- -- tCPf -- -- tREL RES 18 Typ -- -- -- -- -- -- Max 10 5 1000 1000 16 2000 tOSC ns kHz s tW tcyc tsubcyc ms VCC = 4.0 V to 5.5 V VCC = 2.5 V to 5.5 V s ns VCC = 2.7 V to 5.5 V Figure 14.1 2 ns VCC = 2.7 V to 5.5 V 1 Figure 14.1 1 Unit MHz Test Condition VCC = 2.7 V to 5.5 V Reference Figure System clock fOSC oscillation frequency OSC clock (o OSC) cycle time System clock (o) cycle time Subclock oscillation frequency Watch clock cycle time (oW ) Subclock (oSUB) cycle time Instruction cycle time Oscillation stabilization time (crystal oscillator) Oscillation stabilization time External clock high width External clock low width External clock rise time External clock fall time Pin RES low width tOSC 32.768 -- 30.5 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 8 -- 40 60 2 -- -- -- -- 15 20 15 20 -- ns VCC = 2.7 V to 5.5 V Figure 14.1 ns VCC = 2.7 V to 5.5 V Figure 14.1 ns VCC = 2.7 V to 5.5 V Figure 14.1 tcyc tsubcyc Figure 14.2 Notes: 1. A frequency between 1 MHz to 10 MHz is required when an external clock is input. 2. Selected with SA1 and SA0 of system clock control register 2 (SYSCR2). 279 Table 14.3 Control Signal Timing (cont) VCC = 2.2 V to 5.5 V, VSS = 0.0 V, Ta = -20 to +75C, including subactive mode, unless otherwise specified. Item Oscillation start voltage Input pin high width Symbol Vstart Applicable Pins OSC1, OSC2 X1, X2 tIH Min 2.5 2.5 Typ -- -- -- Max -- -- -- tcyc tsubcyc Figure 14.3 Unit V Test Condition Reference Figure IRQ0 to IRQ4, 2 WKP0 to WKP7, ADTRG, TMIF, TMIG IRQ0 to IRQ4, 2 WKP0 to WKP7, ADTRG, TMIF, TMIG Input pin low width tIL -- -- tcyc tsubcyc Figure 14.3 280 Table 14.4 Serial Interface Timing (SCI1) VCC = 2.2 V to 5.5 V, VSS = 0.0 V, Ta = -20 to +75C, including subactive mode, unless otherwise specified. Item Input serial clock cycle time Input serial clock high width Input serial clock low width Input serial clock rise time Input serial clock fall time Serial output data delay time Serial input data setup time Serial input data hold time Symbol tscyc tSCKH tSCKL tSCKr Applicable Pins SCK1 SCK1 SCK1 SCK1 Min 2 0.4 0.4 -- -- tSCKf SCK1 -- -- tSOD SO 1 -- -- tSIS SI 1 200 400 tSIH SI 1 200 400 Typ -- -- -- -- -- -- -- -- -- -- -- -- -- Max -- -- -- 60 80 60 80 200 350 -- -- -- -- ns VCC = 4.0 V to 5.5 V Figure 14.4 ns VCC = 4.0 V to 5.5 V Figure 14.4 ns VCC = 4.0 V to 5.5 V Figure 14.4 ns VCC = 4.0 V to 5.5 V Figure 14.4 Unit tcyc tscyc tscyc ns VCC = 4.0 V to 5.5 V Test Condition Reference Figure Figure 14.4 Figure 14.4 Figure 14.4 Figure 14.4 Table 14.5 Serial Interface Timing (SCI3) VCC = 2.2 V to 5.5 V, VSS = 0.0 V, Ta = -20 to +75C, including subactive mode, unless otherwise specified. Item Input clock cycle Asynchronous Synchronous Input clock pulse width Transmit data delay time (synchronous mode) Receive data setup time (synchronous mode) Receive data hold time (synchronous mode) tSCKW tTXD Symbol tscyc Min 4 6 0.4 -- -- tRXS 200 400 tRXH 200 400 Typ -- -- -- -- -- -- -- -- -- Max -- -- 0.6 1 1 -- -- -- -- ns VCC = 4.0 V to 5.5 V Figure 14.6 ns VCC = 4.0 V to 5.5 V Figure 14.6 tscyc tcyc VCC = 4.0 V to 5.5 V Figure 14.5 Figure 14.6 Unit tcyc Test Condition Reference Figure Figure 14.5 281 14.2.4 A/D Converter Characteristics Table 14.6 shows the A/D converter characteristics. Table 14.6 A/D Converter Characteristics VCC = 2.2 V to 5.5 V, VSS = 0.0 V, Ta = -20 to +75C, unless otherwise specified. Item Analog input voltage Analog input capacitance Allowable signal source impedance Resolution Non-linearity error Quantization error Absolute accuracy Conversion time Symbol AV IN CAIN RAIN Applicable Pins AN6, AN 7 AN6, AN 7 Min -0.3 -- -- Typ -- -- -- Max VCC + 0.3 30 10 Unit V pF k Test Condition Notes -- -- -- -- 12.4 24.8 -- -- -- -- -- -- 8 bit LSB LSB LSB s s VCC = 4.5 V to 5.5 V 2.0 0.5 2.5 248 248 282 14.2.5 DTMF Characteristics Table 14.7 lists the DTMF generator characteristics. Table 14.7 DTMF Characteristics VCC = 2.2 V to 5.5 V, VSS = 0.0 V, Ta = -20 to +75C, unless otherwise specified Item Reference level supply voltage DTMF output voltage (row) Symbol VTref VOR Applicable Pins VTref TONED TONED Min 2.2 550 567 -- -- Typ -- 723 760 3 2.5 Max Unit Test Condition Notes VCC + 0.3 V -- -- 7 -- mVrms VTref - GND = 2.2 V Figure 14.8 RL = 100 k 1 mVrms VTref - GND = 2.2 V Figure 14.8 RL = 100 k 1 % dB VTref - GND = 2.2 V Figure 14.8 RL = 100 k VTref - GND = 2.2 V Figure 14.8 RL = 100 k DTMF output VOC voltage (column) DTMF output distortion DTMF output level %DISDT TONED dBCR TONED Notes: 1. V OR and VOC indicate the output voltage during single wave output. 283 14.3 Operation Timing Figures 14.1 to 14.6 show operation timings. t OSC VIH OSC1 VIL t CPH t CPr t CPL t CPf Figure 14.1 System Clock Input Timing RES VIL tREL Figure 14.2 RES Low Width Timing IRQ0 to IRQ 4 WKP0 to WKP7 ADTRG TMIF, TMIG VIH VIL t IL t IH Figure 14.3 Input Timing 284 t Scyc V IH or V OH* SCK 1 V IL or V OL * t SCKL t SCKf t SOD t SCKH t SCKr VOH* SO 1 VOL * t SIS t SIH SI 1 Notes: * Output timing reference levels Output high: VOH = 2.0 V Output low: VOL = 0.8 V Refer to figure 14.7 for output load condition. Figure 14.4 Serial Interface 1 Input/Output Timing 285 t SCKW SCK 3 t Scyc Figure 14.5 SCK3 Input Clock Timing t Scyc V IH or V OH* SCK 3 V IL or V OL * t TXD TXD (transmit data) VOH * VOL* t RXS RXD (receive data) Notes: * Output timing reference levels Output high: VOH = 2.0 V Output low: VOL = 0.8 V Refer to figure 14.7 for output load condition. t RXH Figure 14.6 Input/Output Timing of Serial Interface 3 in Synchronous Mode 286 14.4 Output Load Circuits Figure 14.7 shows an output load condition. VCC 2.4 k Output pin 30 pF 12 k Figure 14.7 Output Load Condition RL = 100 k TONED GND Figure 14.8 TONED Load Circuit 287 288 Appendix A CPU Instruction Set A.1 Instructions Operation Notation Rd8/16 Rs8/16 Rn8/16 CCR N Z V C PC SP #xx: 3/8/16 d: 8/16 @aa: 8/16 + - x / -- General register (destination) (8 or 16 bits) General register (source) (8 or 16 bits) General register (8 or 16 bits) Condition code register N (negative) flag in CCR Z (zero) flag in CCR V (overflow) flag in CCR C (carry) flag in CCR Program counter Stack pointer Immediate data (3, 8, or 16 bits) Displacement (8 or 16 bits) Absolute address (8 or 16 bits) Addition Subtraction Multiplication Division Logical AND Logical OR Exclusive logical OR Move Logical complement Condition Code Notation Symbol Modified according to the instruction result * 0 -- Undefined (value not guaranteed) Always cleared to 0 Not affected by the instruction execution result 289 Table A.1 lists the H8/300L CPU instruction set. Table A.1 Instruction Set Addressing Mode/ Instruction Length (Bytes) Condition Code Operand Size #xx: 8/16 Rn Mnemonic Operation I HNZVC MOV.B #xx:8, Rd MOV.B Rs, Rd MOV.B @Rs, Rd MOV.B @(d:16, Rs), Rd MOV.B @Rs+, Rd MOV.B @aa:8, Rd MOV.B @aa:16, Rd MOV.B Rs, @Rd MOV.B Rs, @(d:16, Rd) MOV.B Rs, @-Rd MOV.B Rs, @aa:8 MOV.B Rs, @aa:16 MOV.W #xx:16, Rd MOV.W Rs, Rd MOV.W @Rs, Rd 2 2 2 4 2 2 4 2 4 2 2 4 4 2 2 4 2 4 2 4 2 4 2 ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- B #xx:8 Rd8 B Rs8 Rd8 B @Rs16 Rd8 B @(d:16, Rs16) Rd8 B @Rs16 Rd8 Rs16+1 Rs16 B @aa:8 Rd8 B @aa:16 Rd8 B Rs8 @Rd16 B Rs8 @(d:16, Rd16) B Rd16-1 Rd16 Rs8 @Rd16 B Rs8 @aa:8 B Rs8 @aa:16 W #xx:16 Rd W Rs16 Rd16 W @Rs16 Rd16 W @Rs16 Rd16 Rs16+2 Rs16 W @aa:16 Rd16 W Rs16 @Rd16 W Rd16-2 Rd16 Rs16 @Rd16 W Rs16 @aa:16 W @SP Rd16 SP+2 SP 0--2 0--2 0--4 0--6 0--6 0--4 0--6 0--4 0--6 0--6 0--4 0--6 0--4 0--2 0--4 0--6 0--6 0--6 0--4 0--6 0--6 0--6 0--6 MOV.W @(d:16, Rs), Rd W @(d:16, Rs16) Rd16 MOV.W @Rs+, Rd MOV.W @aa:16, Rd MOV.W Rs, @Rd MOV.W Rs, @(d:16, Rd) W Rs16 @(d:16, Rd16) MOV.W Rs, @-Rd MOV.W Rs, @aa:16 POP Rd 290 No. of States @Rn @(d:16, Rn) @-Rn/@Rn+ @aa: 8/16 @(d:8, PC) @@aa Implied Table A.1 Instruction Set (cont) Addressing Mode/ Instruction Length (Bytes) Operand Size @Rn @(d:16, Rn) @-Rn/@Rn+ Condition Code No. of States #xx: 8/16 Rn Mnemonic Operation @aa: 8/16 @(d:8, PC) @@aa Implied IHNZVC ---- -- PUSH Rs ADD.B #xx:8, Rd ADD.B Rs, Rd ADD.W Rs, Rd ADDX.B #xx:8, Rd ADDX.B Rs, Rd ADDS.W #1, Rd ADDS.W #2, Rd INC.B Rd DAA.B Rd SUB.B Rs, Rd SUB.W Rs, Rd SUBX.B #xx:8, Rd SUBX.B Rs, Rd SUBS.W #1, Rd SUBS.W #2, Rd DEC.B Rd DAS.B Rd NEG.B Rd CMP.B #xx:8, Rd CMP.B Rs, Rd CMP.W Rs, Rd MULXU.B Rs, Rd W SP-2 SP Rs16 @SP B Rd8+#xx:8 Rd8 B Rd8+Rs8 Rd8 W Rd16+Rs16 Rd16 B Rd8+#xx:8 +C Rd8 B Rd8+Rs8 +C Rd8 W Rd16+1 Rd16 W Rd16+2 Rd16 B Rd8+1 Rd8 B Rd8 decimal adjust Rd8 B Rd8-Rs8 Rd8 W Rd16-Rs16 Rd16 B Rd8-#xx:8 -C Rd8 B Rd8-Rs8 -C Rd8 W Rd16-1 Rd16 W Rd16-2 Rd16 B Rd8-1 Rd8 B Rd8 decimal adjust Rd8 B 0-Rd Rd B Rd8-#xx:8 B Rd8-Rs8 W Rd16-Rs16 B Rd8 x Rs8 Rd16 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 0--6 2 2 2 2 2 -- -- (1) -- -- (2) (2) ------------ 2 ------------ 2 ---- --* -- --2 * (3) 2 2 2 2 2 -- (1) -- -- (2) (2) ------------ 2 ------------ 2 ---- --* -- -- -- --2 *--2 2 2 2 2 -- (1) -- -- -- -- -- -- 14 291 Table A.1 Instruction Set (cont) Addressing Mode/ Instruction Length (Bytes) Condition Code Operand Size #xx: 8/16 Rn Mnemonic Operation I HNZVC DIVXU.B Rs, Rd AND.B #xx:8, Rd AND.B Rs, Rd OR.B #xx:8, Rd OR.B Rs, Rd XOR.B #xx:8, Rd XOR.B Rs, Rd NOT.B Rd SHAL.B Rd B Rd16/Rs8 Rd16 (RdH: remainder, RdL: quotient) B Rd8#xx:8 Rd8 B Rd8Rs8 Rd8 B Rd8#xx:8 Rd8 B Rd8Rs8 Rd8 B Rd8#xx:8 Rd8 B Rd8Rs8 Rd8 B Rd Rd B C b7 b0 0 2 2 2 2 -- -- (5) (6) -- -- 14 ---- 0--2 0--2 0--2 0--2 0--2 0--2 0--2 2 ---- ---- 2 ---- ---- 2 2 2 ---- ---- ---- 0 SHAR.B Rd B b7 b0 C 2 ---- SHLL.B Rd B C b7 b0 0 2 ---- 0 SHLR.B Rd B 0 b7 b0 C 2 ---- 0 0 ROTXL.B Rd B C b7 b0 2 ---- 0 ROTXR.B Rd B b7 b0 C 2 ---- 0 ROTL.B Rd B C b7 b0 C b7 b0 2 ---- 0 ROTR.B Rd B 2 ---- 0 292 No. of States 2 2 2 2 2 2 2 2 @Rn @(d:16, Rn) @-Rn/@Rn+ @aa: 8/16 @(d:8, PC) @@aa Implied Table A.1 Instruction Set (cont) Addressing Mode/ Instruction Length (Bytes) Condition Code Operand Size #xx: 8/16 Rn Mnemonic Operation I HNZVC BSET #xx:3, Rd BSET #xx:3, @Rd BSET #xx:3, @aa:8 BSET Rn, Rd BSET Rn, @Rd BSET Rn, @aa:8 BCLR #xx:3, Rd BCLR #xx:3, @Rd BCLR #xx:3, @aa:8 BCLR Rn, Rd BCLR Rn, @Rd BCLR Rn, @aa:8 BNOT #xx:3, Rd BNOT #xx:3, @Rd BNOT #xx:3, @aa:8 BNOT Rn, Rd BNOT Rn, @Rd BNOT Rn, @aa:8 BTST #xx:3, Rd BTST #xx:3, @Rd BTST #xx:3, @aa:8 BTST Rn, Rd BTST Rn, @Rd BTST Rn, @aa:8 B (#xx:3 of Rd8) 1 B (#xx:3 of @Rd16) 1 B (#xx:3 of @aa:8) 1 B (Rn8 of Rd8) 1 B (Rn8 of @Rd16) 1 B (Rn8 of @aa:8) 1 B (#xx:3 of Rd8) 0 B (#xx:3 of @Rd16) 0 B (#xx:3 of @aa:8) 0 B (Rn8 of Rd8) 0 B (Rn8 of @Rd16) 0 B (Rn8 of @aa:8) 0 B (#xx:3 of Rd8) (#xx:3 of Rd8) B (#xx:3 of @Rd16) (#xx:3 of @Rd16) B (#xx:3 of @aa:8) (#xx:3 of @aa:8) B (Rn8 of Rd8) (Rn8 of Rd8) B (Rn8 of @Rd16) (Rn8 of @Rd16) B (Rn8 of @aa:8) (Rn8 of @aa:8) B (#xx:3 of Rd8) Z B (#xx:3 of @Rd16) Z B (#xx:3 of @aa:8) Z B (Rn8 of Rd8) Z B (Rn8 of @Rd16) Z B (Rn8 of @aa:8) Z 2 4 4 2 4 4 2 4 4 2 4 4 2 4 4 2 4 4 2 4 4 2 4 4 ------------ 2 ------------ 8 ------------ 8 ------------ 2 ------------ 8 ------------ 8 ------------ 2 ------------ 8 ------------ 8 ------------ 2 ------------ 8 ------------ 8 ------------ 2 ------------ 8 ------------ 8 ------------ 2 ------------ 8 ------------ 8 ------ ------ ------ ------ ------ ------ ---- 2 ---- 6 ---- 6 ---- 2 ---- 6 ---- 6 293 No. of States @Rn @(d:16, Rn) @-Rn/@Rn+ @aa: 8/16 @(d:8, PC) @@aa Implied Table A.1 Instruction Set (cont) Addressing Mode/ Instruction Length (Bytes) Condition Code Operand Size #xx: 8/16 Rn Mnemonic Operation I HNZVC BLD #xx:3, Rd BLD #xx:3, @Rd BLD #xx:3, @aa:8 BILD #xx:3, Rd BILD #xx:3, @Rd BILD #xx:3, @aa:8 BST #xx:3, Rd BST #xx:3, @Rd BST #xx:3, @aa:8 BIST #xx:3, Rd BIST #xx:3, @Rd BIST #xx:3, @aa:8 BAND #xx:3, Rd BAND #xx:3, @Rd BAND #xx:3, @aa:8 BIAND #xx:3, Rd BIAND #xx:3, @Rd BIAND #xx:3, @aa:8 BOR #xx:3, Rd BOR #xx:3, @Rd BOR #xx:3, @aa:8 BIOR #xx:3, Rd BIOR #xx:3, @Rd BIOR #xx:3, @aa:8 BXOR #xx:3, Rd BXOR #xx:3, @Rd BXOR #xx:3, @aa:8 BIXOR #xx:3, Rd 2 4 4 2 4 4 2 4 4 2 4 4 2 4 4 2 4 4 2 4 4 2 4 4 2 4 4 2 ---------- ---------- ---------- ---------- ---------- ---------- B (#xx:3 of Rd8) C B (#xx:3 of @Rd16) C B (#xx:3 of @aa:8) C B (#xx:3 of Rd8) C B (#xx:3 of @Rd16) C B (#xx:3 of @aa:8) C B C (#xx:3 of Rd8) B C (#xx:3 of @Rd16) B C (#xx:3 of @aa:8) B C (#xx:3 of Rd8) B C (#xx:3 of @Rd16) B C (#xx:3 of @aa:8) B C(#xx:3 of Rd8) C B C(#xx:3 of @Rd16) C B C(#xx:3 of @aa:8) C B C(#xx:3 of Rd8) C B C(#xx:3 of @Rd16) C B C(#xx:3 of @aa:8) C B C(#xx:3 of Rd8) C B C(#xx:3 of @Rd16) C B C(#xx:3 of @aa:8) C B C(#xx:3 of Rd8) C B C(#xx:3 of @Rd16) C B C(#xx:3 of @aa:8) C B C(#xx:3 of Rd8) C B C(#xx:3 of @Rd16) C B C(#xx:3 of @aa:8) C B C(#xx:3 of Rd8) C ------------ 2 ------------ 8 ------------ 8 ------------ 2 ------------ 8 ------------ 8 ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- 2 6 6 2 6 6 2 6 6 2 6 6 2 6 6 2 294 No. of States 2 6 6 2 6 6 @Rn @(d:16, Rn) @-Rn/@Rn+ @aa: 8/16 @(d:8, PC) @@aa Implied Table A.1 Instruction Set (cont) Addressing Mode/ Instruction Length (Bytes) Condition Code Operand Size Implied Branching Condition #xx: 8/16 Rn Mnemonic Operation I HNZVC BIXOR #xx:3, @Rd BIXOR #xx:3, @aa:8 BRA d:8 (BT d:8) BRN d:8 (BF d:8) BHI d:8 BLS d:8 BCC d:8 (BHS d:8) BCS d:8 (BLO d:8) BNE d:8 BEQ d:8 BVC d:8 BVS d:8 BPL d:8 BMI d:8 BGE d:8 BLT d:8 BGT d:8 BLE d:8 JMP @Rn JMP @aa:16 JMP @@aa:8 BSR d:8 4 4 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 4 2 2 ---------- ---------- B C(#xx:3 of @Rd16) C B C(#xx:3 of @aa:8) C -- PC PC+d:8 -- PC PC+2 -- If -- condition is true -- then -- PC PC+d:8 -- else next; -- -- -- -- -- -- -- -- -- -- PC Rn16 -- PC aa:16 -- PC @aa:8 -- SP-2 SP PC @SP PC PC+d:8 -- SP-2 SP PC @SP PC Rn16 -- SP-2 SP PC @SP PC aa:16 CZ=0 CZ=1 C=0 C=1 Z=0 Z=1 V=0 V=1 N=0 N=1 NV = 0 NV = 1 Z (NV) = 0 Z (NV) = 1 ------------ 4 ------------ 4 ------------ 4 ------------ 4 ------------ 4 ------------ 4 ------------ 4 ------------ 4 ------------ 4 ------------ 4 ------------ 4 ------------ 4 ------------ 4 ------------ 4 ------------ 4 ------------ 4 ------------ 4 ------------ 6 ------------ 8 ------------ 6 JSR @Rn 2 ------------ 6 JSR @aa:16 4 ------------ 8 295 No. of States 6 6 @Rn @(d:16, Rn) @-Rn/@Rn+ @aa: 8/16 @(d:8, PC) @@aa Table A.1 Instruction Set (cont) Addressing Mode/ Instruction Length (Bytes) Condition Code Operand Size #xx: 8/16 Rn Mnemonic Operation I HNZVC JSR @@aa:8 SP-2 SP PC @SP PC @aa:8 -- PC @SP SP+2 SP -- CCR @SP SP+2 SP PC @SP SP+2 SP -- Transit to sleep mode. B #xx:8 CCR B Rs8 CCR B CCR Rd8 B CCR#xx:8 CCR B CCR#xx:8 CCR B CCR#xx:8 CCR -- PC PC+2 -- if R4L0 then Repeat @R5 @R6 R5+1 R5 R6+1 R6 R4L-1 R4L Until R4L=0 else next; 2 2 2 2 2 2 2 ------------ 8 RTS RTE 2 ------------ 8 2 10 SLEEP LDC #xx:8, CCR LDC Rs, CCR STC CCR, Rd ANDC #xx:8, CCR ORC #xx:8, CCR XORC #xx:8, CCR NOP EEPMOV 2 ------------ 2 ------------ 2 2 ------------ 2 4 -- -- -- -- -- -- (4) Notes: (1) Set to 1 when there is a carry or borrow from bit 11; otherwise cleared to 0. (2) If the result is zero, the previous value of the flag is retained; otherwise the flag is cleared to 0. (3) Set to 1 if decimal adjustment produces a carry; otherwise retains value prior to arithmetic operation. (4) The number of states required for execution is 4n + 9 (n = value of R4L). (5) Set to 1 if the divisor is negative; otherwise cleared to 0. (6) Set to 1 if the divisor is zero; otherwise cleared to 0. 296 No. of States 2 2 2 2 2 @Rn @(d:16, Rn) @-Rn/@Rn+ @aa: 8/16 @(d:8, PC) @@aa Implied A.2 Operation Code Map Table A.2 is an operation code map. It shows the operation codes contained in the first byte of the instruction code (bits 15 to 8 of the first instruction word). Instruction when first bit of byte 2 (bit 7 of first instruction word) is 0. Instruction when first bit of byte 2 (bit 7 of first instruction word) is 1. 297 ; ; ; ;; ; Table A.2 2 ADD SUB DEC SUBS CMP INC ADDS MOV ADDX SUBX 3 4 5 6 7 8 9 A B C D E F DAA DAS STC LDC ORC XORC ANDC LDC ROTXL ROTXR NOT OR XOR AND ROTL ROTR NEG MOV 298 BVS JMP MOV * MOV EEPMOV Bit-manipulation instructions BPL BMI BGE BLT BGT JSR BLE Low High 0 1 0 NOP SLEEP SHLL SHLR 1 SHAL SHAR 2 3 Operation Code Map 4 BRA BRN BHI BLS BCC BCS BNE BEQ BVC 5 MULXU DIVXU RTS BSR RTE BST 6 BSET BNOT BCLR BTST BOR BXOR BAND BIST BLD 7 BIOR BIXOR BIAND BILD 8 ADD 9 ADDX A CMP B SUBX C OR D XOR E AND F MOV Note: * The PUSH and POP instructions are identical in machine language to MOV instructions. A.3 Number of Execution States The following describes the operation status in each instruction provided for the H8/300 L CPU, as well as a calculation of the number of execution states. Table A.4 gives the number of cycles (as the operation status) for such operations as an instruction fetch, data read/write performed during an instruction execution. Table A.3 gives the number of execution states required for each cycle (operation status). The total number of states required for the execution of an instruction can be calculated by using the following equation: Execution states = I x S I + J x S J + K x S K + L x S L + M x S M + N x S N Examples: When instruction is fetched from on-chip ROM, and an on-chip RAM is accessed. 1. BSET #0, @FF00 From table A.4: I = L = 2, J = K = M = N= 0 From table A.3: S I = 2, SL = 2 Number of states required for execution = 2 x 2 + 2 x 2 = 8 When instruction is fetched from on-chip ROM, branch address is read from on-chip ROM, and on-chip RAM is used for stack area. 2. JSR @@ 30 From table A.4: I = 2, J = K = 1, From table A.3: S I = SJ = SK = 2 Number of states required for execution = 2 x 2 + 1 x 2+ 1 x 2 = 8 L=M=N=0 299 Table A.3 Number of Cycles in Each Instruction Access Location On-Chip Memory SI SJ SK SL SM SN 1 2 or 3* -- 1 2 On-Chip Peripheral Module -- Execution Status (Instruction Cycle) Instruction fetch Branch address read Stack operation Byte data access Word data access Internal operation Note: * Depends on which on-chip module is accessed. See 2.9.1, Notes on Data Access for details. 300 Table A.4 Number of Cycles in Each Instruction Instruction Branch Stack Byte Data Fetch Addr. Read Operation Access I J K L 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 2 2 1 2 2 1 1 Word Data Internal Access Operation M N Instruction Mnemonic ADD ADD.B #xx:8, Rd ADD.B Rs, Rd ADD.W Rs, Rd ADDS ADDS.W #1, Rd ADDS.W #2, Rd ADDX ADDX.B #xx:8, Rd ADDX.B Rs, Rd AND AND.B #xx:8, Rd AND.B Rs, Rd ANDC BAND ANDC #xx:8, CCR BAND #xx:3, Rd BAND #xx:3, @Rd BAND #xx:3, @aa:8 Bcc BRA d:8 (BT d:8) BRN d:8 (BF d:8) BHI d:8 BLS d:8 BCC d:8 (BHS d:8) BCS d:8 (BLO d:8) BNE d:8 BEQ d:8 BVC d:8 BVS d:8 BPL d:8 BMI d:8 BGE d:8 BLT d:8 BGT d:8 BLE d:8 BCLR BCLR #xx:3, Rd BCLR #xx:3, @Rd BCLR #xx:3, @aa:8 BCLR Rn, Rd 301 Table A.4 Number of Cycles in Each Instruction (cont) Instruction Branch Stack Byte Data Fetch Addr. Read Operation Access I J K L 2 2 1 2 1 1 2 2 Word Data Internal Access Operation M N Instruction Mnemonic BCLR BCLR Rn, @Rd BCLR Rn, @aa:8 BIAND BIAND #xx:3, Rd BIAND #xx:3, @Rd BIAND #xx:3, @aa:8 2 BILD BILD #xx:3, Rd BILD #xx:3, @Rd BILD #xx:3, @aa:8 BIOR BIOR #xx:3, Rd BIOR #xx:3, @Rd BIOR #xx:3, @aa:8 BIST BIST #xx:3, Rd BIST #xx:3, @Rd BIST #xx:3, @aa:8 BIXOR BIXOR #xx:3, Rd BIXOR #xx:3, @Rd 1 2 2 1 2 2 1 2 2 1 2 1 1 1 1 2 2 1 1 BIXOR #xx:3, @aa:8 2 BLD BLD #xx:3, Rd BLD #xx:3, @Rd BLD #xx:3, @aa:8 BNOT BNOT #xx:3, Rd BNOT #xx:3, @Rd BNOT #xx:3, @aa:8 BNOT Rn, Rd BNOT Rn, @Rd BNOT Rn, @aa:8 BOR BOR #xx:3, Rd BOR #xx:3, @Rd BOR #xx:3, @aa:8 BSET BSET #xx:3, Rd BSET #xx:3, @Rd BSET #xx:3, @aa:8 BSET Rn, Rd BSET Rn, @Rd 1 2 2 1 2 2 1 2 2 1 2 2 1 2 2 1 2 1 1 2 2 2 2 1 1 2 2 2 302 Table A.4 Number of Cycles in Each Instruction (cont) Instruction Branch Stack Byte Data Fetch Addr. Read Operation Access I J K L Word Data Internal Access Operation M N Instruction Mnemonic BSET BSR BST BSET Rn, @aa:8 BSR d:8 BST #xx:3, Rd BST #xx:3, @Rd 2 2 1 2 1 1 2 2 2 1 1 1 1 1 1 BST #xx:3, @aa:8 2 BTST BTST #xx:3, Rd BTST #xx:3, @Rd 2 BTST #xx:3, @aa:8 2 BTST Rn, Rd BTST Rn, @Rd BTST Rn, @aa:8 BXOR BXOR #xx:3, Rd BXOR #xx:3, @aa:8 CMP CMP. B Rs, Rd CMP.W Rs, Rd DAA DAS DEC DIVXU INC JMP DAA.B Rd DAS.B Rd DEC.B Rd DIVXU.B Rs, Rd INC.B Rd JMP @Rn JMP @aa:16 JMP @@aa:8 JSR JSR @Rn JSR @aa:16 JSR @@aa:8 LDC LDC #xx:8, CCR LDC Rs, CCR 1 2 2 1 2 BXOR #xx:3, @Rd 2 CMP. B #xx:8, Rd 1 1 1 1 1 1 1 2 1 2 2 2 2 2 2 1 1 1 1 1 1 1 2 2 2 2n+2* 12 1 EEPMOV EEPMOV Note: n: Initial value in R4L. The source and destination operands are accessed n + 1 times each. 303 Table A.4 Number of Cycles in Each Instruction (cont) Instruction Branch Stack Byte Data Fetch Addr. Read Operation Access I J K L Word Data Internal Access Operation M N Instruction Mnemonic MOV MOV.B #xx:8, Rd MOV.B Rs, Rd MOV.B @Rs, Rd 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 MOV.B @(d:16, Rs), 2 Rd MOV.B @Rs+, Rd MOV.B @aa:8, Rd MOV.B @aa:16, Rd MOV.B Rs, @Rd MOV.B Rs, @(d:16, Rd) MOV.B Rs, @-Rd MOV.B Rs, @aa:8 MOV.B Rs, @aa:16 MOV.W #xx:16, Rd MOV.W Rs, Rd MOV.W @Rs, Rd 1 1 2 1 2 1 1 2 2 1 1 1 1 1 1 1 1 1 1 12 2 2 MOV.W @(d:16, Rs), 2 Rd MOV.W @Rs+, Rd 1 MOV.W @aa:16, Rd 2 MOV.W Rs, @Rd 1 MOV.W Rs, @(d:16, 2 Rd) MOV.W Rs, @-Rd 1 MOV.W Rs, @aa:16 2 MULXU NEG NOP NOT OR MULXU.B Rs, Rd NEG.B Rd NOP NOT.B Rd OR.B #xx:8, Rd OR.B Rs, Rd ORC ROTL ROTR ORC #xx:8, CCR ROTL.B Rd ROTR.B Rd 1 1 1 1 1 1 1 1 1 304 Table A.4 Number of Cycles in Each Instruction (cont) Instruction Branch Stack Byte Data Fetch Addr. Read Operation Access I J K L 1 1 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 1 2 2 Word Data Internal Access Operation M N Instruction Mnemonic ROTXL ROTXR RTE RTS SHAL SHAR SHLL SHLR SLEEP STC SUB ROTXL.B Rd ROTXR.B Rd RTE RTS SHAL.B Rd SHAR.B Rd SHLL.B Rd SHLR.B Rd SLEEP STC CCR, Rd SUB.B Rs, Rd SUB.W Rs, Rd SUBS SUBS.W #1, Rd SUBS.W #2, Rd POP PUSH SUBX POP Rd PUSH Rs SUBX.B #xx:8, Rd SUBX.B Rs, Rd XOR XOR.B #xx:8, Rd XOR.B Rs, Rd XORC XORC #xx:8, CCR 305 Appendix B On-Chip Registers B.1 I/O Registers (1) Bit Names Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name Address Register (Low) Name Bit 7 H'90 H'91 H'92 H'93 H'94 H'95 H'96 H'97 H'98 H'99 H'9A H'9B H'9C H'9D H'9E H'9F H'A0 H'A1 H'A2 H'A3 H'A4 H'A5 H'A6 H'A7 H'A8 H'A9 H'AA SMR BRR SCR3 COM BRR7 TIE PMR1 PMR2 PMR6 PMR5 PUCR1 PUCR2 PUCR5 PUCR6 SCR1 SCSR1 SDRU SDRL IRQ3 IRQ0 -- WKP7 IRQ2 -- -- WKP6 IRQ1 POF1 -- WKP5 -- NCS -- WKP4 TMIG SO1 -- WKP3 TMOFH TMOFL SI1 TXD WKP2 SCK1 -- WKP1 TMOW IRQ4 -- WKP0 I/O ports PUCR17 PUCR16 PUCR15 PUCR14 PUCR13 PUCR12 PUCR11 PUCR10 PUCR27 PUCR26 PUCR25 PUCR24 PUCR23 PUCR22 PUCR21 PUCR20 PUCR57 PUCR56 PUCR55 PUCR54 PUCR53 PUCR52 PUCR51 PUCR50 PUCR67 PUCR66 PUCR65 PUCR64 PUCR63 PUCR62 PUCR61 PUCR60 SNC1 -- SDRU7 SDRL7 SNC0 SOL SDRU6 SDRL6 -- ORER SDRU5 SDRL5 -- -- SDRU4 SDRL4 CKS3 -- SDRU3 SDRL3 CKS2 -- SDRU2 SDRL2 CKS1 -- SDRU1 SDRL1 CKS0 STF SDRU0 SDRL0 SCI1 CHR BRR6 RIE PE BRR5 TE PM BRR4 RE STOP BRR3 MPIE MP BRR2 TEIE CKS1 BRR1 CKE1 CKS0 BRR0 CKE0 SCI3 Legend: SCI1: Serial communication interface 1 SCI3: Serial communication interface 3 306 Address Register (Low) Name Bit 7 H'AB H'AC H'AD H'AE H'AF H'B0 H'B1 H'B2 H'B3 H'B4 H'B5 H'B6 H'B7 H'B8 H'B9 H'BA H'BB H'BC H'BD H'BE H'BF H'C0 H'C1 H'C2 H'C3 H'C4 H'C5 H'C6 H'C7 H'C8 H'C9 H'CA H'CB H'CC AMR ADRR ADSR CKS ADR7 ADSF TCRF TCSRF TCFH TCFL OCRFH OCRFL TMG ICRGF ICRGR TOLH OVFH TCFH7 TCFL7 TMA TCA DTCR DTLR TMA7 TCA7 DTEN -- TDR SSR RDR TDR7 TDRE RDR7 Bit Names Bit 6 TDR6 RDRF RDR6 Bit 5 TDR5 OER RDR5 Bit 4 TDR4 FER RDR4 Bit 3 TDR3 PER RDR3 Bit 2 TDR2 TEND RDR2 Bit 1 TDR1 MPBR RDR1 Bit 0 TDR0 MPBT RDR0 Module Name SCI3 TMA6 TCA6 -- -- TMA5 TCA5 CLOE -- -- TCA4 RWOE DTL4 TMA3 TCA3 CLF1 DTL3 TMA2 TCA2 CLF0 DTL2 TMA1 TCA1 RWF1 DTL1 TMA0 TCA0 RWF0 DTL0 Timer A DTMF generator CKSH2 CMFH TCFH6 TCFL6 CKSH1 OVIEH TCFH5 TCFL5 CKSH0 CCLRH TCFH4 TCFL4 TOLL OVFL TCFH3 TCFL3 CKSL2 CMFL TCFH2 TCFL2 CKSL1 OVIEL TCFH1 TCFL1 CKSL0 CCLRL TCFH0 TCFL0 Timer F OCRFH7 OCRFH6 OCRFH5 OCRFH4 OCRFH3 OCRFH2 OCRFH1 OCRFH0 OCRFL7 OCRFL6 OCRFL5 OCRFL4 OCRFL3 OCRFL2 OCRFL1 OCRFL0 OVFH OVFL OVIE IIEGS CCLR1 CCLR0 CKS1 CKS0 Timer G ICRGF7 ICRGF6 ICRGF5 ICRGF4 ICRGF3 ICRGF2 ICRGF1 ICRGF0 ICRGR7 ICRGR6 ICRGR5 ICRGR4 ICRGR3 ICRGR2 ICRGR1 ICRGR0 TRGE ADR6 -- CKS1 ADR5 -- -- ADR4 -- CH3 ADR3 -- CH2 ADR2 -- CH1 ADR1 -- CH0 ADR0 -- A/D converter 307 Address Register (Low) Name Bit 7 H'CD H'CE H'CF H'D0 H'D1 H'D2 H'D3 H'D4 H'D5 H'D6 H'D7 H'D8 H'D9 H'DA H'DB H'DC H'DD H'DE H'DF H'E0 H'E1 H'E2 H'E3 H'E4 H'E5 H'E6 H'E7 H'E8 H'E9 H'EA H'EB H'EC H'ED PCRA -- PCR5 PCR6 PCR7 PCR8 PCR57 PCR67 PCR77 PCR87 PCR1 PCR2 PCR17 PCR27 PDRA PDRB -- PB 7 PDR5 PDR6 PDR7 PDR8 P57 P67 P77 P87 PDR1 PDR2 P17 P27 Bit Names Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name I/O ports P16 P26 P15 P25 P14 P24 P13 P23 P12 P22 P11 P21 P10 P20 P56 P66 P76 P86 P55 P65 P75 P85 P54 P64 P74 P84 P53 P63 P73 P83 P52 P62 P72 P82 P51 P61 P71 P81 P50 P60 P70 P80 I/O ports -- PB 6 -- -- -- -- PA 3 -- PA 2 -- PA 1 -- -- -- I/O ports PCR16 PCR26 PCR15 PCR25 PCR14 PCR24 PCR13 PCR23 PCR12 PCR22 PCR11 PCR21 PCR10 PCR20 PCR56 PCR66 PCR76 PCR86 PCR55 PCR65 PCR75 PCR85 PCR54 PCR64 PCR74 PCR84 PCR53 PCR63 PCR73 PCR83 PCR52 PCR62 PCR72 PCR82 PCR51 PCR61 PCR71 PCR81 PCR50 PCR60 PCR70 PCR80 I/O ports -- -- -- PCRA3 PCRA2 PCRA1 -- 308 Address Register (Low) Name Bit 7 H'EE H'EF H'F0 H'F1 H'F2 H'F3 H'F4 H'F5 H'F6 H'F7 H'F8 H'F9 H'FA H'FB H'FC H'FD H'FE H'FF IWPR IWPF7 IRR1 IRR2 IRRTA IRRDT SYSCR1 SSBY SYSCR2 -- IEGR IENR1 IENR2 -- IENTA IENDT Bit Names Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name STS2 -- -- IENS1 IENAD STS1 -- -- IENWP -- STS0 NESEL IEG4 IEN4 IENTG LSON DTON IEG3 IEN3 -- MSON IEG2 IEN2 -- SA1 IEG1 IEN1 -- -- SA0 IEG0 IEN0 -- System control IENTFH IENTFL IRRS1 IRRAD -- -- IRRI4 IRRTG IRRI3 IRRI2 IRRI1 -- IRRI0 -- IRRTFH IRRTFL System control IWPF6 IWPF5 IWPF4 IWPF3 IWPF2 IWPF1 IWPF0 System control 309 B.2 I/O Registers (2) Register name Address to which the register is mapped Name of on-chip supporting module Register acronym MTCR--Multitone control register H'90 Multitone generator Bit numbers Bit 7 DA0E Initial value Read/Write 0 R/W 6 MTEN 0 R/W 5 DIR 0 R/W 4 -- 1 -- 3 FR1 0 -- 2 FR0 0 R/W 1 FT1 0 R/W 0 FT0 0 R/W Initial bit values Names of the bits. Dashes (--) indicate reserved bits. Possible types of access R W Read only Write only Fine-tuning counter clock source select FT1 0 0 1 1 FT0 0 1 0 1 Clock Division Ratio 1tOSC (counter clock = fOSC) 2tOSC (counter clock = fOSC/2) 4tOSC (counter clock = fOSC/4) 8tOSC (counter clock = fOSC/8) R/W Read and write Full name of bit Frame counter clock source select FR1 FR0 0 0 0 1 1 0 1 1 Clock Division Ratio 1tOSC (counter clock = fOSC) 2tOSC (counter clock = fOSC/2) 4tOSC (counter clock = fOSC/4) 8tOSC (counter clock = fOSC/8) Descriptions of bit settings 310 PMR1--Port mode register 1 Bit Initial value Read/Write 7 IRQ3 0 R/W 6 IRQ2 0 R/W 5 IRQ1 0 R/W 4 -- 0 -- 3 H'98 2 TMOFH 0 R/W 1 TMOFL 0 R/W I/O ports 0 TMOW 0 R/W TMIG 0 R/W P10 /TMOW pin function switch 0 Functions as P10 I/O pin 1 Functions as TMOW output pin P11 /TMOFL pin function switch 0 Functions as P11 I/O pin 1 Functions as TMOFL output pin P12 /TMOFH pin function switch 0 Functions as P12 I/O pin 1 Functions as TMOFH output pin P13 /TMIG pin function switch 0 Functions as P13 I/O pin 1 Functions as TMIG input pin P15 /IRQ 1 pin function switch 0 Functions as P15 I/O pin 1 Functions as IRQ 1 input pin P16 /IRQ 2 pin function switch 0 Functions as P16 I/O pin 1 Functions as IRQ 2 input pin P17 /IRQ 3 /TMIF pin function switch 0 Functions as P17 I/O pin 1 Functions as IRQ 3 /TMIF input pin 311 PMR2--Port mode register 2 Bit Initial value Read/Write 7 IRQ0 0 R/W 6 -- 1 -- 5 POF1 0 R/W 4 NCS 0 R/W 3 H'99 2 SI1 0 R/W 1 SCK1 0 R/W I/O ports 0 IRQ4 0 R/W SO1 0 R/W P20 /IRQ 4 /ADTRG pin function switch 0 Functions as P20 I/O pin 1 Functions as IRQ 4 /ADTRG input pin P21 /SCK 1 pin function switch 0 Functions as P21 I/O pin 1 Functions as SCK 1 I/O pin P22 /SI 1 pin function switch 0 Functions as P2 2 I/O pin 1 Functions as SI 1 input pin P23 /SO 1 pin function switch 0 Functions as P2 3 I/O pin 1 Functions as SO 1 output pin TMIG noise canceller select 0 Noise canceller function not selected 1 Noise canceller function selected P23 /SO 1 pin PMOS control 0 CMOS output 1 NMOS open drain output P27 /IRQ 0 pin function switch 0 Functions as P27 input pin 1 Functions as IRQ 0 input pin 312 PMR6--Port mode register 6 Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 R/W 4 -- 1 R/W 3 H'9A 2 TXD 0 R/W 1 -- 0 R/W I/O ports 0 -- 0 R/W -- 1 -- P26/TXD pin function switch 0 Functions as P26 I/O pin 1 Functions as TXD output pin PMR5--Port mode register 5 Bit Initial value Read/Write 7 WKP 7 0 R/W 6 WKP 6 0 R/W 5 WKP 5 0 R/W 4 WKP 4 0 R/W 3 H'9B 2 WKP 2 0 R/W 1 WKP 1 0 R/W I/O ports 0 WKP 0 0 R/W WKP 3 0 R/W P5n /WKPn pin function switch 0 Functions as P5 n I/O pin 1 Functions as WKPn input pin (n = 7 to 0) PUCR1--Port pull-up control register 1 Bit Initial value Read/Write 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 H'9C 2 0 R/W 1 0 R/W I/O ports 0 0 R/W PUCR17 PUCR16 PUCR15 PUCR14 PUCR13 PUCR12 PUCR11 PUCR10 R/W PUCR2--Port pull-up control register 2 Bit Initial value Read/Write 7 0 R/W 6 0 R/W 5 0 R/W 4 PUCR4 0 R/W 3 H'9D 2 PUCR2 0 R/W 1 PUCR1 0 R/W I/O ports 0 PUCR0 0 R/W PUCR27 PUCR26 PUCR5 PUCR3 0 R/W 313 PUCR5--Port pull-up control register 5 Bit Initial value Read/Write 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 H'9E 2 0 R/W 1 0 R/W I/O ports 0 0 R/W PUCR57 PUCR56 PUCR55 PUCR54 PUCR53 PUCR52 PUCR51 PUCR50 R/W PUCR6--Port pull-up control register 6 Bit Initial value Read/Write 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 H'9F 2 0 R/W 1 0 R/W I/O ports 0 0 R/W PUCR67 PUCR66 PUCR65 PUCR64 PUCR63 PUCR62 PUCR61 PUCR60 R/W 314 SCR1--Serial control register 1 Bit Initial value Read/Write 7 SNC1 0 R/W 6 SNC0 0 R/W 5 -- 0 R/W 4 -- 0 R/W 3 H'A0 2 CKS2 0 R/W 1 CKS1 0 R/W 0 SCI1 CKS3 0 R/W CKS0 0 R/W Clock select Bit 2 Bit 1 Bit 0 CKS2 CKS1 CKS0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Transfer Clock Cycle Synchronous Prescaler Division o = 5 MHz o = 2.5 MHz 204.8 s 409.6 s o/1024 51.2 s 102.4 s o/256 12.8 s 25.6 s o/64 6.4 s 12.8 s o/32 3.2 s 6.4 s o/16 1.6 s 3.2 s o/8 0.8 s 1.6 s o/4 -- 0.8 s o/2 Clock source select 0 Clock source is prescaler S, and pin SCK 1 is output pin 1 Clock source is external clock, and pin SCK 1 is input pin Operation mode select 0 0 8-bit synchronous mode 1 16-bit synchronous mode 1 0 Continuous clock output mode 1 Reserved 315 SCSR1--Serial control/status register 1 Bit Initial value Read/Write 7 -- 1 -- 6 SOL 0 R/W 5 ORER 0 R/(W)* 4 -- 1 -- 3 -- 1 -- H'A1 2 -- 1 -- 1 -- 0 R 0 SCI1 STF 0 R/W Start flag 0 Read Write 1 Read Write Indicates that transfer is stopped Invalid Indicates transfer in progress Starts a transfer operation Overrun error flag 0 [Clearing condition] After reading 1, cleared by writing 0 1 [Setting condition] Set if a clock pulse is input after transfer is complete, when an external clock is used Extended data bit 0 Read SO1 pin output level is low Write SO1 pin output level changes to low 1 Read SO1 pin output level is high Write SO1 pin output level changes to high Note: * Only a write of 0 for flag clearing is possible. SDRU--Serial data register U Bit Initial value Read/Write 7 SDRU7 R/W 6 SDRU6 R/W 5 SDRU5 R/W 4 SDRU4 R/W 3 H'A2 2 SDRU2 R/W 1 SDRU1 R/W 0 SCI1 SDRU3 R/W SDRU0 R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Stores transmit and receive data 8-bit transfer mode: Not used 16-bit transfer mode: Upper 8 bits of data 316 SDRL--Serial data register L Bit Initial value Read/Write 7 SDRL7 R/W 6 SDRL6 R/W 5 SDRL5 R/W 4 SDRL4 R/W 3 H'A3 2 SDRL2 R/W 1 SDRL1 R/W 0 SCI1 SDRL3 R/W SDRL0 R/W Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Stores transmit and receive data 8-bit transfer mode: 8-bit data 16-bit transfer mode: Lower 8 bits of data SMR--Serial mode register Bit Initial value Read/Write 7 COM 0 R/W 6 CHR 0 R/W 5 PE 0 R/W 4 PM 0 R/W 3 H'A8 2 MP 0 R/W 1 CKS1 0 R/W 0 SCI3 STOP 0 R/W CKS0 0 R/W Multiprocessor mode 0 Multiprocessor communication function disabled 1 Multiprocessor communication function enabled Stop bit length 0 1 stop bit 1 2 stop bits Parity mode 0 Even parity 1 Odd parity Parity enable 0 Parity bit adding and checking disabled 1 Parity bit adding and checking enabled Character length 0 8-bit data 1 7-bit data Communication mode 0 Asynchronous mode 1 Synchronous mode Clock select 0, 1 0 0 o clock 1 o/4 clock 1 0 o/16 clock 1 o/64 clock 317 BRR--Bit rate register Bit Initial value Read/Write 7 BRR7 1 R/W 6 BRR6 1 R/W 5 BRR5 1 R/W 4 BRR4 1 R/W 3 H'A9 2 BRR2 1 R/W 1 BRR1 1 R/W 0 SCI3 BRR3 1 R/W BRR0 1 R/W 318 SCR3--Serial control register 3 Bit Initial value Read/Write 7 TIE 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W 3 H'AA 2 TEIE 0 R/W 1 CKE1 0 R/W 0 SCI3 MPIE 0 R/W CKE0 0 R/W Clock enable Bit 1 CKE1 0 Bit 0 CKE0 0 1 1 0 1 Transmit end interrupt enable 0 1 Transmit end interrupt (TEI) disabled Transmit end interrupt (TEI) enabled Communication Mode Asynchronous Synchronous Asynchronous Synchronous Asynchronous Synchronous Asynchronous Synchronous Description Clock Source Internal clock Internal clock Internal clock Reserved External clock External clock Reserved Reserved SCK 3 Pin Function I/O port Serial clock output Clock output Reserved Clock output Serial clock input Reserved Reserved Multiprocessor interrupt enable 0 Multiprocessor interrupt request disabled (ordinary receive operation) [Clearing condition] Multiprocessor bit receives a data value of 1 Multiprocessor interrupt request enabled Until a multiprocessor bit value of 1 is received, the receive data full interrupt (RXI) and receive error interrupt (ERI) are disabled, and serial status register (SSR) flags RDRF, FER, and OER are not set. 1 Receive enable 0 1 Receive operation disabled (RXD is a general I/O port) Receive operation enabled (RXD is the receive data pin) Transmit enable 0 1 Transmit operation disabled (TXD is the transmit data pin) Transmit operation enabled (TXD is the transmit data pin) Receive interrupt enable 0 1 Receive data full interrupt request (RXI) and receive error interrupt request (ERI) disabled Receive data full interrupt request (RXI) and receive error interrupt request (ERI) enabled Transmit interrupt enable 0 1 Transmit data empty interrupt request (TXI) disabled Transmit data empty interrupt request (TXI) enabled 319 TDR--Transmit data register Bit Initial value Read/Write 7 TDR7 1 R/W 6 TDR6 1 R/W 5 TDR5 1 R/W 4 TDR4 1 R/W 3 H'AB 2 TDR2 1 R/W 1 TDR1 1 R/W 0 SCI3 TDR3 1 R/W TDR0 1 R/W Data to be transferred to TSR 320 SSR--Serial status register Bit Initial value Read/Write 7 TDRE 1 R/(W)* 6 RDRF 0 R/(W)* 5 OER 0 R/(W)* 4 FER 0 R/(W)* 3 H'AC 2 TEND 1 R 1 MPBR 0 R 0 SCI3 PER 0 R/(W)* MPBT 0 R/W Multiprocessor bit receive 0 Indicates reception of data in which the multiprocessor bit is 0 1 Indicates reception of data in which the multiprocessor bit is 1 Multiprocessor bit transmit 0 The multiprocessor bit in transmit data is 0 1 The multiprocessor bit in transmit data is 1 Transmit end 0 Indicates that transmission is in progress [Clearing conditions] * After reading TDRE = 1, cleared by writing 0 to TDRE. * When data is written to TDR by an instruction. 1 Indicates that a transmission has ended [Setting conditions] * When bit TE in serial control register 3 (SCR3) is 0. * If TDRE is set to 1 when the last bit of a transmitted character is sent. Parity error 0 Indicates that data receiving is in progress or has been completed [Clearing conditions] After reading PER = 1, cleared by writing 0 1 Indicates that a parity error occurred in data receiving [Setting conditions] When the sum of 1s in received data plus the parity bit does not match the parity mode bit (PM) setting in the serial mode register (SMR) Framing error 0 Indicates that data receiving is in progress or has been completed [Clearing conditions] After reading FER = 1, cleared by writing 0 1 Indicates that a framing error occurred in data receiving [Setting conditions] The stop bit at the end of receive data is checked and found to be 0 Overrun error 0 Indicates that data receiving is in progress or has been completed [Clearing conditions] After reading OER = 1, cleared by writing 0 1 Indicates that an overrun error occurred in data receiving [Setting conditions] When data receiving is completed while RDRF is set to 1 Receive data register full 0 Indicates there is no receive data in RDR [Clearing conditions] * After reading RDRF = 1, cleared by writing 0. * When data is read from RDR by an instruction. 1 Indicates that there is receive data in RDR [Setting conditions] When receiving ends normally, with receive data transferred from RSR to RDR Transmit data register empty 0 Indicates that transmit data written to TDR has not been transferred to TSR [Clearing conditions] * After reading TDRE = 1, cleared by writing 0. * When data is written to TDR by an instruction. 1 Indicates that no transmit data has been written to TDR, or the transmit data written to TDR has been transferred to TSR [Setting conditions] * When bit TE in serial control register 3 (SCR3) is 0. * When data is transferred from TDR to TSR. Note: * Only a write of 0 for flag clearing is possible. 321 RDR--Receive data register Bit Initial value Read/Write 7 RDR7 0 R 6 RDR6 0 R 5 RDR5 0 R 4 RDR4 0 R 3 H'AD 2 RDR2 0 R 1 RDR1 0 R 0 SCI3 RDR3 0 R RDR0 0 R TMA--Timer mode register A Bit Initial value Read/Write 7 TMA7 0 R/W 6 TMA6 0 R/W 5 TMA5 0 R/W 4 -- 1 -- H'B0 3 TMA3 0 R/W 2 TMA2 0 R/W 1 TMA1 0 R/W Timer A 0 TMA0 0 R/W Clock output select 0 0 0 o/32 1 o/16 1 0 o/8 1 o/4 1 0 0 o W /32 1 o W /16 1 0 o W /8 1 o W /4 Internal clock select Prescaler and Divider Ratio TMA3 TMA2 TMA1 TMA0 or Overflow Period 0 0 0 o/8192 0 PSS 1 o/4096 PSS o/2048 PSS 1 0 o/512 PSS 1 1 0 0 o/256 PSS 1 o/128 PSS o/32 1 0 PSS o/8 1 PSS 0 0 0 1s 1 PSW 1 0.5 s PSW 0.25 s 1 0 PSW 0.03125 s 1 PSW 1 0 0 PSW and TCA are reset 1 1 0 1 Function Interval timer Time base 322 TCA--Timer counter A Bit Initial value Read/Write 7 TCA7 0 R 6 TCA6 0 R 5 TCA5 0 R 4 TCA4 0 R H'B1 3 TCA3 0 R 2 TCA2 0 R 1 TCA1 0 R Timer A 0 TCA0 0 R Count value 323 DTCR--DTMF control register Bit Initial value Read/Write 7 DTEN 0 R/W 6 -- 1 -- 5 CLOE 0 R/W 4 RWOE 0 R/W 3 H'B2 2 CLF0 0 R/W DTMF generator 1 RWF1 0 R/W 0 RWF0 0 R/W CLF1 0 R/W DTMF row signal output frequency 1 and 0 RWF1 RWF0 0 0 1 1 0 1 DTMF row signal output frequency 697 Hz (R1) 770 Hz (R2) 852 Hz (R3) 941 Hz (R4) DTMF column signal output frequency 1 and 0 CLF1 CLF0 DTMF column signal output frequency 1209 Hz (C1) 0 0 1336 Hz (C2) 1 1447 Hz (C3) 0 1 1633 Hz (C4) 1 Row output enable 0 DTMF row signal output is disabled (high-impedance) 1 DTMF row signal output is enabled Column output enable 0 DTMF column signal output is disabled (high-impedance) 1 DTMF column signal output is enabled DTMF generator enable 0 DTMF generator is halted 1 DTMF generator operates 324 DTLR--DTMF load register Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 DTL4 0 R/W H'B3 3 DTL3 0 R/W 2 DTL2 0 R/W DTMF generator 1 DTL1 0 R/W 0 DTL0 0 R/W OSC clock division ratio 4 to 0 DTL4 DTL3 DTL2 DTL1 DTL0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 1 1 1 Note: * Don't care ... 1 1 1 ... 0 0 1 ... 0 1 * ... 1 * * ... Division Ratio Illegal setting Illegal setting Illegal setting 3 4 25 Illegal setting Illegal setting ... OSC Clock Frequency (initial value) 1.2 MHz 1.6 MHz 10 MHz ... 325 TCRF--Timer control register F Bit Initial value Read/Write 7 TOLH 0 W 6 CKSH2 0 W 5 CKSH1 0 W 4 CKSH0 0 W 3 H'B6 2 CKSL2 0 W 1 CKSL1 0 W Timer F 0 CKSL0 0 W TOLL 0 W Toggle output level H 0 Low level 1 High level Clock select L 0 * * External event (TMIF): Rising or falling edge 1 0 0 Internal clock: o/32 1 Internal clock: o/16 1 0 Internal clock: o/4 1 Internal clock: o/2 Toggle output level L 0 Low level 1 High level Clock select H 0 * * 16-bit mode selected. TCFL overflow signals are counted. 1 0 0 Internal clock: o/32 1 Internal clock: o/16 1 0 Internal clock: o/4 1 Internal clock: o/2 Note: * Don't care 326 TCSRF--Timer control/status register F Bit Initial value Read/Write 7 OVFH 0 R/(W) 6 CMFH 0 R/(W) 5 OVIEH 0 R/W 4 CCLRH 0 R/W 3 H'B7 2 CMFL 0 R/(W) 1 OVIEL 0 R/W Timer F 0 CCLRL 0 R/W OVFL 0 R/(W) Timer overflow interrupt enable L 0 TCFL overflow interrupt disabled 1 TCFL overflow interrupt enabled Compare match flag L 0 [Clearing condition] After reading CMFL = 1, cleared by writing 0 to CMFL 1 [Setting condition] When the TCFL value matches the OCRFL value Timer overflow flag L 0 [Clearing condition] After reading OVFL = 1, cleared by writing 0 to OVFL 1 [Setting condition] When the value of TCFL goes from H'FF to H'00 Counter clear H 0 16-bit mode: 8-bit mode: 1 16-bit mode: 8-bit mode: TCF clearing by compare match disabled TCFH clearing by compare match disabled TCF clearing by compare match enabled TCFH clearing by compare match enabled Counter clear L 0 TCFL clearing by compare match disabled 1 TCFL clearing by compare match enabled Timer overflow interrupt enable H 0 TCFH overflow interrupt disabled 1 TCFH overflow interrupt enabled Compare match flag H 0 [Clearing condition] After reading CMFH = 1, cleared by writing 0 to CMFH 1 [Setting condition] When the TCFH value matches the OCRFH value Timer overflow flag H 0 [Clearing condition] After reading OVFH = 1, cleared by writing 0 to OVFH 1 [Setting condition] When the value of TCFH goes from H'FF to H'00 327 TCFH--8-bit timer counter FH Bit Initial value Read/Write 7 TCFH7 0 R/W 6 TCFH6 0 R/W 5 TCFH5 0 R/W 4 TCFH4 0 R/W H'B8 3 TCFH3 0 R/W 2 TCFH2 0 R/W 1 TCFH1 0 R/W Timer F 0 TCFH0 0 R/W Count value TCFL--8-bit timer counter FL Bit Initial value Read/Write 7 TCFL7 0 R/W 6 TCFL6 0 R/W 5 TCFL5 0 R/W 4 TCFL4 0 R/W H'B9 3 TCFL3 0 R/W 2 TCFL2 0 R/W 1 TCFL1 0 R/W Timer F 0 TCFL0 0 R/W Count value OCRFH--Output compare register FH Bit Initial value Read/Write 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W H'BA 3 1 R/W 2 1 R/W 1 1 R/W Timer F 0 1 R/W OCRFH7 OCRFH6 OCRFH5 OCRFH4 OCRFH3 OCRFH2 OCRFH1 OCRFH0 OCRFL--Output compare register FL Bit Initial value Read/Write 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W H'BB 3 1 R/W 2 1 R/W 1 1 R/W Timer F 0 1 R/W OCRFL7 OCRFL6 OCRFL5 OCRFL4 OCRFL3 OCRFL2 OCRFL1 OCRFL0 328 TMG--Timer mode register G Bit Initial value Read/Write 7 OVFH 0 R/(W)* 6 OVFL 0 R/(W)* 5 OVIE 0 R/W 4 IIEGS 0 R/W H'BC 3 CCLR1 0 R/W 2 CCLR0 0 R/W 1 CKS1 0 R/W Timer G 0 CKS0 0 R/W Counter clear 0 0 TCG is not cleared 1 TCG is cleared at the falling edge of the input capture signal 1 0 TCG is cleared at the rising edge of the input capture signal 1 TCG is cleared at both edges of the input capture signal Clock select 0 0 Internal clock: 1 Internal clock: 1 0 Internal clock: 1 Internal clock: o/64 o/32 o/2 o W /2 Input capture interrupt edge select 0 Interrupts are requested at the rising edge of the input capture signal 1 Interrupts are requested at the falling edge of the input capture signal Timer overflow interrupt enable 0 TCG overflow interrupt disabled 1 TCG overflow interrupt enabled Timer overflow flag L 0 [Clearing condition] After reading OVFL = 1, cleared by writing 0 to OVFL 1 [Setting condition] When the value of TCG overflows from H'FF to H'00 Timer overflow flag H 0 [Clearing condition] After reading OVFH = 1, cleared by writing 0 to OVFH 1 [Setting condition] When the value of TCG overflows from H'FF to H'00 Note: * Only a write of 0 for flag clearing is possible. 329 ICRGF--Input capture register GF Bit Initial value Read/Write 7 0 R 6 0 R 5 0 R 4 0 R H'BD 3 0 R 2 0 R 1 0 R Timer G 0 0 R ICRGF7 ICRGF6 ICRGF5 ICRGF4 ICRGF3 ICRGF2 ICRGF1 ICRGF0 ICRGR--Input capture register GR Bit Initial value Read/Write 7 0 R 6 0 R 5 0 R 4 0 R H'BE 3 0 R 2 0 R 1 0 R Timer G 0 0 R ICRGR7 ICRGR6 ICRGR5 ICRGR4 ICRGR3 ICRGR2 ICRGR1 ICRGR0 330 AMR--A/D mode register Bit Initial value Read/Write 7 CKS 0 R/W 6 TRGE 0 R/W 5 CKS1 0 R/W 4 -- 1 -- 3 H'C4 2 CH2 0 R/W 1 A/D converter 0 CH0 0 R/W CH3 0 R/W CH1 0 R/W Channel select Bit 3 Bit 2 Bit 1 CH3 CH2 CH1 0 0 * 1 * 1 0 0 1 1 External trigger select * Bit 0 CH0 * * * 0 1 * Analog input channel No channel selected Reserved Reserved AN 6 AN 7 Reserved * Don't care 0 Disables start of A/D conversion by external trigger 1 Enables start of A/D conversion by rising or falling edge of external trigger at pin ADTRG Clock select Bit 7 Bit 5 CKS CKS1 0 0 1 0 1 0 1 1 Conversion Time o = 2 MHz o = 5 MHz -- 62 s 31 s 15.5 s -- 24.8 s 12.4 s --* Conversion Period Reserved 124/o 62/o 31/o Note: * Operation is not guaranteed if the conversion time is less than 12.4 s. Set bits 5 and 7 for a value of at least 12.4 s. ADRR--A/D result register Bit Initial value Read/Write 7 ADR7 R 6 ADR6 R 5 ADR5 R 4 ADR4 R H'C5 3 ADR3 R 2 ADR2 R 1 A/D converter 0 ADR0 R ADR1 R Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined A/D conversion result 331 ADSR--A/D start register Bit Initial value Read/Write 7 ADSF 0 R/W 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 H'C6 2 -- 1 -- 1 -- 1 -- A/D converter 0 -- 1 -- -- 1 -- A/D start flag 0 [Read] Indicates the completion of A/D conversion [Write] Stops A/D conversion 1 [Read] Indicates A/D conversion in progress [Write] Starts A/D conversion PDR1--Port data register 1 Bit Initial value Read/Write 7 P17 0 R/W 6 P16 0 R/W 5 P15 0 R/W 4 P14 0 R/W 3 H'D4 2 P12 0 R/W 1 P11 0 R/W I/O ports 0 P10 0 R/W P13 0 R/W PDR2--Port data register 2 Bit Initial value Read/Write 7 P27 0 R/W 6 P26 0 R/W 5 P25 0 R/W 4 P24 0 R/W 3 H'D5 2 P22 0 R/W 1 P21 0 R/W I/O ports 0 P20 0 R/W P23 0 R/W PDR5--Port data register 5 Bit Initial value Read/Write 7 P5 7 0 R/W 6 P56 0 R/W 5 P55 0 R/W 4 P54 0 R/W 3 H'D8 2 P52 0 R/W 1 P51 0 R/W I/O ports 0 P50 0 R/W P53 0 R/W 332 PDR6--Port data register 6 Bit Initial value Read/Write 7 P6 7 0 R/W 6 P66 0 R/W 5 P6 5 0 R/W 4 P64 0 R/W 3 H'D9 2 P6 2 0 R/W 1 P6 1 0 R/W I/O ports 0 P6 0 0 R/W P6 3 0 R/W PDR7--Port data register 7 Bit Initial value Read/Write 7 P7 7 0 R/W 6 P76 0 R/W 5 P75 0 R/W 4 P74 0 R/W 3 H'DA 2 P72 0 R/W 1 P71 0 R/W I/O ports 0 P70 0 R/W P73 0 R/W PDR8--Port data register 8 Bit Initial value Read/Write 7 P8 7 0 R/W 6 P86 0 R/W 5 P8 5 0 R/W 4 P84 0 R/W 3 H'DB 2 P8 2 0 R/W 1 P8 1 0 R/W I/O ports 0 P8 0 0 R/W P8 3 0 R/W PDRA--Port data register A Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 H'DD 2 PA 2 0 R/W 1 PA 1 0 R/W I/O ports 0 -- 0 -- PA3 0 R/W PDRB--Port data register B Bit Initial value Read/Write R R -- -- 7 PB 7 6 PB 6 5 -- 4 -- 3 H'DE 2 -- -- 1 -- -- I/O ports 0 -- -- -- -- 333 PCR1--Port control register 1 Bit Initial value Read/Write 7 PCR17 0 W 6 PCR16 0 W 5 PCR15 0 W 4 PCR14 0 W 3 H'E4 2 PCR12 0 W 1 PCR11 0 W I/O ports 0 PCR10 0 W PCR13 0 W Port 1 input/output select 0 Input pin 1 Output pin PCR2--Port control register 2 Bit Initial value Read/Write 7 PCR27 0 W 6 PCR26 0 W 5 PCR25 0 W 4 PCR24 0 W 3 H'E5 2 PCR22 0 W 1 PCR21 0 W I/O ports 0 PCR20 0 W PCR23 0 W Port 2 input/output select 0 Input pin 1 Output pin Note: As P27 is an input-only pin, it becomes a high-impedance output when PCR27 is set to 1. PCR5--Port control register 5 Bit Initial value Read/Write 7 PCR57 0 W 6 PCR56 0 W 5 PCR55 0 W 4 PCR54 0 W 3 H'E8 2 PCR52 0 W 1 PCR51 0 W I/O ports 0 PCR50 0 W PCR53 0 W Port 5 input/output select 0 Input pin 1 Output pin 334 PCR6--Port control register 6 Bit Initial value Read/Write 7 PCR67 0 W 6 PCR66 0 W 5 PCR65 0 W 4 PCR64 0 W 3 H'E9 2 PCR62 0 W 1 PCR61 0 W I/O ports 0 PCR60 0 W PCR63 0 W Port 6 input/output select 0 Input pin 1 Output pin PCR7--Port control register 7 Bit Initial value Read/Write 7 PCR77 0 W 6 PCR76 0 W 5 PCR75 0 W 4 PCR74 0 W 3 H'EA 2 PCR72 0 W 1 PCR71 0 W I/O ports 0 PCR70 0 W PCR73 0 W Port 7 input/output select 0 Input pin 1 Output pin PCR8--Port control register 8 Bit Initial value Read/Write 7 PCR87 0 W 6 PCR86 0 W 5 PCR85 0 W 4 PCR84 0 W 3 H'EB 2 PCR82 0 W 1 PCR81 0 W I/O ports 0 PCR80 0 W PCR83 0 W Port 8 input/output select 0 Input pin 1 Output pin 335 PCRA--Port control register A Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 H'ED 2 PCRA 2 0 W 1 PCRA 1 0 W I/O ports 0 -- 1 -- PCRA 3 0 W Port A input/output select 0 Input pin 1 Output pin SYSCR1--System control register 1 Bit Initial value Read/Write 7 SSBY 0 R/W 6 STS2 0 R/W 5 STS1 0 R/W 4 STS0 0 R/W 3 H'F0 2 -- 1 -- 1 System control 0 -- 1 -- LSON 0 R/W -- 1 -- Low speed on flag 0 The CPU operates on the system clock (o) 1 The CPU operates on the subclock (oSUB ) Standby timer select 2 to 0 0 0 0 Wait time = 8,192 states 1 Wait time = 16,384 states 1 0 Wait time = 32,768 states 1 Wait time = 65,536 states 1 * * Wait time = 131,072 states Software standby 0 When a SLEEP instruction is executed in active mode, a transition is made to sleep mode. When a SLEEP instruction is executed in subactive mode, a transition is made to subsleep mode. 1 When a SLEEP instruction is executed in active mode, a transition is made to standby mode or watch mode. When a SLEEP instruction is executed in subactive mode, a transition is made to watch mode. Note: * Don't care 336 SYSCR2--System control register 2 Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 NESEL 0 R/W 3 H'F1 2 MSON 0 R/W 1 System control 0 SA0 0 R/W DTON 0 R/W SA1 0 R/W Medium speed on flag 0 Operates in active (high-speed) mode 1 Operates in active (medium-speed) mode Direct transfer on flag Subactive mode clock select 0 0 o W /8 1 o W /4 1 * o W /2 0 When a SLEEP instruction is executed in active mode, a transition is made to standby mode, watch mode, or sleep mode. When a SLEEP instruction is executed in subactive mode, a transition is made to watch mode or subsleep mode. 1 When a SLEEP instruction is executed in active (high-speed) mode, a direct transition is made to active (medium-speed) mode if SSBY = 0, MSON = 1, and LSON = 0, or to subactive mode if SSBY = 1, TMA3 = 1, and LSON = 1. When a SLEEP instruction is executed in active (medium-speed) mode, a direct transition is made to active (high-speed) mode if SSBY = 0, MSON = 0, and LSON = 0, or to subactive mode if SSBY = 1, TMA3 = 1, and LSON = 1. When a SLEEP instruction is executed in subactive mode, a direct transition is made to active (high-speed) mode if SSBY = 1, TMA3 = 1, LSON = 0, and MSON = 0, or to active (medium-speed) mode if SSBY = 1, TMA3 = 1, LSON = 0, and MSON = 1. Noise elimination sampling frequency select 0 Sampling rate is oOSC /16 1 Sampling rate is oOSC /4 Note: * Don't care 337 IEGR--IRQ edge select register Bit Initial value Read/Write 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 IEG4 0 R/W 3 H'F2 2 IEG2 0 R/W 1 System control 0 IEG0 0 R/W IEG3 0 R/W IEG1 0 R/W IRQ 0 edge select 0 Falling edge of IRQ 0 pin input is detected 1 Rising edge of IRQ 0 pin input is detected IRQ 1 edge select 0 Falling edge of IRQ 1 pin input is detected 1 Rising edge of IRQ 1 pin input is detected IRQ 2 edge select 0 Falling edge of IRQ 2 pin input is detected 1 Rising edge of IRQ 2 pin input is detected IRQ 3 edge select 0 Falling edge of IRQ 3 /TMIF pin input is detected 1 Rising edge of IRQ 3 /TMIF pin input is detected IRQ 4 edge select 0 Falling edge of IRQ 4 /ADTRG pin input is detected 1 Rising edge of IRQ 4 /ADTRG pin input is detected 338 IENR1--Interrupt enable register 1 Bit Initial value Read/Write 7 IENTA 0 R/W 6 IENS1 0 R/W 5 IENWP 0 R/W 4 IEN4 0 R/W 3 H'F3 2 IEN2 0 R/W 1 System control 0 IEN0 0 R/W IEN3 0 R/W IEN1 0 R/W IRQ 4 to IRQ 0 interrupt enable 0 Disables interrupt requests from IRQ 4 to IRQ 0 1 Enables interrupt requests from IRQ 4 to IRQ 0 Wakeup interrupt enable 0 Disables interrupt requests from WKP7 to WKP0 1 Enables interrupt requests from WKP7 to WKP0 SCI1 interrupt enable 0 Disables SCI1 interrupts 1 Enables SCI1 interrupts Timer A interrupt enable 0 Disables timer A interrupts 1 Enables timer A interrupts 339 IENR2--Interrupt enable register 2 Bit Initial value Read/Write 7 IENDT 0 R/W 6 IENAD 0 R/W 5 -- 0 -- 4 IENTG 0 R/W 3 0 R/W H'F4 2 0 R/W 1 -- 0 -- System control 0 -- 1 -- IENTFH IENTFL Timer FL interrupt enable 0 Disables timer FL interrupts 1 Enables timer FL interrupts Timer FH interrupt enable 0 Disables timer FH interrupts 1 Enables timer FH interrupts Timer G interrupt enable 0 Disables timer G interrupts 1 Enables timer G interrupts A/D converter interrupt enable 0 Disables A/D converter interrupt requests 1 Enables A/D converter interrupt requests Direct transfer interrupt enable 0 Disables direct transfer interrupt requests 1 Enables direct transfer interrupt requests 340 IRR1--Interrupt request register 1 Bit Initial value Read/Write 7 IRRTA 0 R/W * 6 IRRS1 0 R/W * 5 -- 1 -- 4 IRRI4 0 R/W * 3 H'F6 2 IRRI2 0 R/W * 1 System control 0 IRRI0 0 R/W * IRRI3 0 R/W * IRRI1 0 R/W * IRQ 4 to IRQ 0 interrupt request flag 0 [Clearing condition] When IRRIn = 1, it is cleared by writing 0 to IRRIn. 1 [Setting condition] When pin IRQ n is set to interrupt input and the designated signal edge is detected. SCI1 interrupt request flag 0 [Clearing condition] When IRRS1 = 1, it is cleared by writing 0 1 [Setting condition] When an SCI1 transfer is completed Timer A interrupt request flag 0 [Clearing condition] When IRRTA = 1, it is cleared by writing 0 1 [Setting condition] When the timer A counter overflows from H'FF to H'00 Note: * Only a write of 0 for flag clearing is possible. (n = 4 to 0) 341 IRR2--Interrupt request register 2 Bit Initial value Read/Write 7 IRRDT 0 R/W * 6 IRRAD 0 R/W * 5 -- 0 -- 4 IRRTG 0 R/W * H'F7 3 0 R/W * 2 0 R/W * System control 1 -- 0 -- 0 -- 1 -- IRRTFH IRRTFL Timer FL interrupt request flag 0 [Clearing condition] When IRRTFL = 1, it is cleared by writing 0 1 [Setting condition] When TCFL matches in 8-bit mode Timer FH interrupt request flag 0 [Clearing condition] When IRRTFH = 1, it is cleared by writing 0 1 [Setting condition] When counter FH matches output compare register FH in 8-bit mode, or when 16-bit counter F (TCFL, TCFH) matches 16-bit output compare register F (OCRFL, OCRFH) in 16-bit mode Timer G interrupt request flag 0 [Clearing condition] When IRRTG = 1, it is cleared by writing 0 1 [Setting condition] When pin TMIG is set to TMIG input and the designated signal edge is detected A/D converter interrupt request flag 0 [Clearing condition] When IRRAD = 1, it is cleared by writing 0 1 [Setting condition] When A/D conversion is completed and ADSF is reset Direct transfer interrupt request flag 0 [Clearing condition] When IRRDT = 1, it is cleared by writing 0 1 [Setting condition] A SLEEP instruction is executed when DTON = 1 and a direct transfer is made Note: * Only a write of 0 for flag clearing is possible. 342 IWPR--Wakeup interrupt request register Bit Initial value Read/Write 7 IWPF7 0 R/W * 6 IWPF6 0 R/W * 5 IWPF5 0 R/W * 4 IWPF4 0 R/W * 3 H'F9 2 IWPF2 0 R/W * 1 System control 0 IWPF0 0 R/W * IWPF3 0 R/W * IWPF1 0 R/W * Wakeup interrupt request flag 0 [Clearing condition] When IWPFn = 1, it is cleared by writing 0. 1 [Setting condition] When pin WKPn is set to interrupt input and a falling signal edge is detected. (n = 7 to 0) Note: * Only a write of 0 for flag clearing is possible. 343 Appendix C I/O Port Block Diagrams C.1 Port 1 Block Diagrams SBY (low level during reset and in standby mode) Internal data bus PUCR17 VCC VCC PMR17 P17 PDR17 VSS PCR17 Timer F module TMIF IRQ3 PDR1: PCR1: PMR1: PUCR1: Port data register 1 Port control register 1 Port mode register 1 Port pull-up control register 1 Figure C.1 (a) Port 1 Block Diagram (Pin P1 7) 344 SBY (low level during reset and in standby mode) Internal data bus PUCR16 VCC VCC PMR16 P16 PDR16 VSS PCR16 IRQ2 PDR1: PCR1: PMR1: PUCR1: Port data register 1 Port control register 1 Port mode register 1 Port pull-up control register 1 Figure C.1 (b) Port 1 Block Diagram (Pin P16) 345 SBY (low level during reset and in standby mode) Internal data bus PUCR15 VCC VCC PMR15 P15 PDR15 VSS PCR15 IRQ1 PDR1: PCR1: PMR1: PUCR1: Port data register 1 Port control register 1 Port mode register 1 Port pull-up control register 1 Figure C.1 (c) Port 1 Block Diagram (Pin P15) 346 SBY Internal data bus PUCR14 VCC VCC P14 PDR14 VSS PCR14 PDR1: Port data register 1 PCR1: Port control register 1 PUCR1: Port pull-up control register 1 Figure C.1 (d) Port 1 Block Diagram (Pin P14) 347 SBY Internal data bus PUCR13 VCC VCC PMR13 P13 PDR13 VSS PCR13 Timer G module TMIG PDR1: PCR1: PMR1: PUCR1: Port data register 1 Port control register 1 Port mode register 1 Port pull-up control register 1 Figure C.1 (e) Port 1 Block Diagram (Pin P13) 348 Timer F module TMOFH (P12) TMOFL (P11) SBY Internal data bus PUCR1n VCC PMR1n P1n PDR1n VCC VSS PCR1n PDR1: PCR1: PMR1: PUCR1: n = 2, 1 Port data register 1 Port control register 1 Port mode register 1 Port pull-up control register 1 Figure C.1 (f) Port 1 Block Diagram (Pins P12 and P11) 349 Timer A module TMOW SBY Internal data bus PUCR10 VCC PMR10 P10 PDR10 VCC VSS PCR10 PDR1: PCR1: PMR1: PUCR1: Port data register 1 Port control register 1 Port mode register 1 Port pull-up control register 1 Figure C.1 (g) Port 1 Block Diagram (Pin P1 0) 350 C.2 Port 2 Block Diagrams Internal data bus PUCR27 PMR2 7 P2 7 PDR27 PCR27 IRQ 0 PDR2: PCR2: PMR2: PUCR2: Port data register 2 Port control register 2 Port mode register 2 Port pull-up control register 2 Figure C.2 (a) Port 2 Block Diagram (Pin P2 7) 351 SBY PMR6 2 VCC PUCR26 P2 6 PDR2 6 SCI3 module TXD VCC Internal data bus VSS PCR2 6 PDR2: PCR2: PMR6: PUCR2: Port data register 2 Port control register 2 Port mode register 6 Port pull-up control register 2 Figure C.2 (b) Port 2 Block Diagram (Pin P26) 352 SBY SCI3 module RE RXD PUCR25 P2 5 PDR2 5 Internal data bus VCC VCC VSS PCR2 5 PDR2: Port data register 2 PCR2: Port control register 2 PUCR2: Port pull-up control register 2 Figure C.2 (c) Port 2 Block Diagram (Pin P25) 353 SCI3 module SBY SCKIE SCKOE SCKO SCKI PUCR24 VCC VCC P2 4 PDR2 4 VSS PCR2 4 PDR2: Port data register 2 PCR2: Port control register 2 PUCR2: Port pull-up control register 2 Figure C.2 (d) Port 2 Block Diagram (Pin P24) 354 Internal data bus SCI1 module SO 1 PMR2 3 Internal data bus PUCR2 3 VCC VCC PMR2 3 P2 3 PDR2 3 SBY VSS PCR2 3 PDR2: Port data register 2 PCR2: Port control register 2 PMR2: Port mode register 2 PUCR2: Port pull-up control register 2 Figure C.2 (e) Port 2 Block Diagram (Pin P23) 355 SBY Internal data bus PUCR22 VCC VCC PMR22 P22 PDR22 VSS PCR22 SCI module SI PDR2: PCR2: PMR2: PUCR2: Port data register 2 Port control register 2 Port mode register 2 Port pull-up control register 2 Figure C.2 (f) Port 2 Block Diagram (Pin P22) 356 SCI module EXCK SCKO SCKI SBY PUCR21 VCC PMR2 1 P2 1 PDR21 Internal data bus VCC VSS PCR21 PDR2: PCR2: PMR2: PUCR2: Port data register 2 Port control register 2 Port mode register 2 Port pull-up control register 2 Figure C.2 (g) Port 2 Block Diagram (Pin P2 1) 357 SBY Internal data bus PUCR2 0 VCC VCC PMR2 0 P20 PDR20 VSS PCR2 0 A/D module ADTRG IRQ 4 PDR2: PCR2: PMR2: PUCR2: Port data register 2 Port control register 2 Port mode register 2 Port pull-up control register 2 Figure C.2 (h) Port 2 Block Diagram (Pin P20) 358 C.3 Port 5 Block Diagram SBY Internal data bus PUCR5n VCC VCC PMR5 n P5 n PDR5n VSS PCR5n WKPn PDR5: PCR5: PMR5: PUCR5: Port data register 5 Port control register 5 Port mode register 5 Port pull-up control register 5 n = 0 to 7 Figure C.3 Port 5 Block Diagram 359 C.4 Port 6 Block Diagram SBY Internal data bus PUCR6n VCC VCC P6 n PDR6n VSS PCR6n PDR6: Port data register 6 PCR6: Port control register 6 PUCR6: Port pull-up control register 6 n = 0 to 7 Figure C.4 Port 6 Block Diagram 360 C.5 Port 7 Block Diagram SBY Internal data bus VCC PDR7n P7n PCR7n VSS PDR7: PCR7: Port data register 7 Port control register 7 n = 0 to 7 Figure C.5 Port 7 Block Diagram 361 C.6 Port 8 Block Diagram SBY Internal data bus VCC PDR8 n P8 n PCR8 n VSS PDR8: Port data register 8 PCR8: Port control register 8 n = 0 to 7 Figure C.6 Port 8 Block Diagram 362 C.7 Port A Block Diagram SBY Internal data bus VCC PDRA n PA n PCRA n VSS PDRA: Port data register A PCRA: Port control register A n = 1 to 3 Figure C.7 Port A Block Diagram C.8 Port B Block Diagram Internal data bus PBn A/D module DEC AMR0 to AMR3 V IN n = 6, 7 Figure C.8 Port B Block Diagram 363 Appendix D Port States in the Different Processing States Table D.1 Port P17 to P1 0 P26 to P2 0 P57 to P5 0 P67 to P6 0 P77 to P7 0 P87 to P8 0 Port States Overview Reset Sleep Subsleep Standby Retained Retained Retained Retained Retained Retained Retained Watch Subactive Active Functional Functional Functional Functional Functional Functional Functional Functional Functional Functional Functional Functional Functional Functional High Retained impedance High Retained impedance High Retained impedance High Retained impedance High Retained impedance High Retained impedance High Retained impedance* High Retained impedance* High Retained impedance* High Retained impedance* High Retained impedance High Retained impedance High Retained impedance PA3 to PA 1 High Retained impedance P27, PB7, PB6 High High High High High High High impedance impedance impedance impedance impedance impedance impedance Note: * High level output when MOS pull-up is in on state. 364 Appendix E Product Line-Up Product Type H8/3627 ZTAT version Product Code Mark Code Standard HD6473627H HD6473627H products HD6473627FP HD6473627FP Package (Hitachi Package Code) 64-pin QFP (FP-64A) 64-pin LQFP (FP-64E) 64-pin QFP (FP-64A) 64-pin LQFP (FP-64E) 64-pin QFP (FP-64A) 64-pin LQFP (FP-64E) 64-pin QFP (FP-64A) 64-pin LQFP (FP-64E) Mask ROM Standard HD6433627H HD6433627(***)H version products HD6433627FP HD6433627(***)FP H8/3626 Mask ROM Standard HD6433626H HD6433626(***)H version products HD6433626FP HD6433626(***)FP Mask ROM Standard HD6433625H HD6433625(***)H version products HD6433625FP HD6433625(***)FP H8/3625 H8/3624S Mask ROM Standard HD6433624SH HD6433624S(***)H 64-pin QFP (FP-64A) version products HD6433624SFP HD6433624S(***)FP 64-pin LQFP (FP-64E) H8/3623S Mask ROM Standard HD6433623SH HD6433623S(***)H 64-pin QFP (FP-64A) version products HD6433623SFP HD6433623S(***)FP 64-pin LQFP (FP-64E) H8/3622S Mask ROM Standard HD6433622SH HD6433622S(***)H 64-pin QFP (FP-64A) version products HD6433622SFP HD6433622S(***)FP 64-pin LQFP (FP-64E) Note: (***) in mask ROM versions is the ROM code. 365 Appendix F Package Dimensions Dimensional drawings of the H8/3627 Series in FP-64A, and FP-64E packages are shown in figure F.1, and F.2, respectively. 17.2 0.3 14 Unit: mm 33 32 48 49 17.2 0.3 64 1 *0.37 0.08 0.35 0.06 17 16 3.05 Max 0.15 M 0.8 *0.17 0.05 0.15 0.04 2.70 1.0 1.6 0 - 8 0.8 0.3 0.10 0.10 +0.15 -0.10 *Dimension including the plating thickness Base material dimension Hitachi Code JEDEC EIAJ Weight (reference value) FP-64A -- Conforms 1.2 g Figure F.1 FP-64A Package Dimensions Note: In case of inconsistencies arising within figures, dimensional drawings listed in the Hitachi Semiconductor Packages Manual take precedence and are considered correct. 366 Unit: mm 12.0 0.2 10 48 33 49 32 12.0 0.2 64 1 *0.22 0.05 0.20 0.04 16 17 1.45 1.25 *0.17 0.05 0.15 0.04 1.70 Max 0.08 M 0.5 1.0 0 - 8 0.5 0.2 0.10 0.10 0.10 *Dimension including the plating thickness Base material dimension Hitachi Code JEDEC EIAJ Weight (reference value) FP-64E -- Conforms 0.4 g Figure F.2 FP-64E Package Dimensions 367 H8/3627 Series Hardware Manual Publication Date: 1st Edition, March 1999 Published by: Electronic Devices Business Group Hitachi, Ltd. Edited by: Technical Documentation Group UL Media Co., Ltd. Copyright (c) Hitachi, Ltd., 1999. All rights reserved. Printed in Japan. |
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